STM32WL55xx STM32WL54xx Multiprotocol LPWAN dual core 32-bit Arm Cortex -M4/M0+ LoRa , (G)FSK, (G)MSK, BPSK, up to 256KB Flash, 64KB SRAM Datasheet - production data Features Includes ST state-of-the-art patented technology UFBGA73 WLCSP59 UFQFPN48 Radio (5 x 5 mm) (7 x 7 mm) Includes ST state-of -the-art patented Active-mode TX: 15 mA at 10 dBm and 87 mA technology at 20 dBm (LoRa 125 kHz) Frequency range: 150 MHz to 960 MHz Core Modulation: LoRa , (G)FSK, (G)MSK and BPSK 32-bit Arm Cortex -M4 CPU RX sensitivity: 123 dBm for 2-FSK Adaptive real-time accelerator (ART (at 1.2 Kbit/s), 148 dBm for LoRa Accelerator) allowing 0-wait-state (at 10.4 kHz, spreading factor 12) execution from Flash memory, frequency up to 48 MHz, MPU and DSP instructions Transmitter high output power, programmable 1.25 DMIPS/MHz (Dhrystone 2.1) up to +22 dBm 32-bit Arm Cortex -M0+ CPU Transmitter low output power, programmable up to +15 dBm Frequency up to 48 MHz, MPU 0.95 DMIPS/MHz (Dhrystone 2.1) Compliant with the following radio frequency regulations such as ETSI EN 300 220, Security and identification EN 300 113, EN 301 166, FCC CFR 47 Part 15, 24, 90, 101 and the Japanese ARIB Hardware encryption AES 256-bit STD-T30, T-67, T-108 True random number generator (RNG) Compatible with standardized or proprietary Sector protection against read/write operations protocols such as LoRaWAN , Sigfox, (PCROP, RDP, WRP) W-MBus and more (fully open wireless system-on-chip) CRC calculation unit Unique device identifier (64-bit UID compliant Ultra-low-power platform with IEEE 802-2001 standard) 1.8 V to 3.6 V power supply 96-bit unique die identifier 40 C to +105 C temperature range Hardware public key accelerator (PKA) Shutdown mode: 31 nA (V = 3 V) DD Key management services Standby (+ RTC) mode: Secure sub-GHz MAC layer 360 nA (V = 3 V) DD Secure firmware update (SFU) Stop2 (+ RTC) mode: 1.07 A (V = 3 V) DD Secure firmware install (SFI) Active-mode MCU: < 72 A/MHz (CoreMark ) Active-mode RX: 4.82 mA July 2021 DS13293 Rev 2 1/147 This is information on a product in full production. www.st.comSTM32WL55/54xx Supply and reset management 12-bit DAC, low-power sample-and-hold 2x ultra-low-power comparators High-efficiency embedded SMPS step-down converter System peripherals SMPS to LDO smart switch Mailbox and semaphores for communication Ultra-safe, low-power BOR (brownout reset) between Cortex -M4 and Cortex -M0+ with 5 selectable thresholds firmware Ultra-low-power POR/PDR Controllers Programmable voltage detector (PVD) V mode with RTC and 20x32-bit backup 2x DMA controller (7 channels each) BAT registers supporting ADC, DAC, SPI, I2C, LPUART, USART, AES and timers Clock sources 2x USART (ISO 7816, IrDA, SPI) 32 MHz crystal oscillator 1x LPUART (low-power) TCXO support: programmable supply voltage 2x SPI 16 Mbit/s (1 over 2 supporting I2S) 32 kHz oscillator for RTC with calibration 3x I2C (SMBus/PMBus) High-speed internal 16 MHz factory trimmed 2x 16-bit 1-channel timer RC ( 1 %) 1x 16-bit 4-channel timer (supporting Internal low-power 32 kHz RC motor control) Internal multi-speed low-power 100 kHz to 1x 32-bit 4-channel timer 48 MHz RC 3x 16-bit ultra-low-power timer PLL for CPU, ADC and audio clocks 1x RTC with 32-bit sub-second wakeup counter Memories 1x independent SysTick 256-Kbyte Flash memory 1x independent watchdog 64-Kbyte RAM 1x window watchdog 20x32-bit backup register Bootloader supporting USART and SPI Up to 43 I/Os, most 5 V-tolerant interfaces Development support OTA (over-the-air) firmware update capable Serial-wire debug (SWD), JTAG Sector protection against read/write operations Dual CPU cross trigger capabilities Rich analog peripherals (down to 1.62 V) All packages ECOPACK2 compliant 12-bit ADC 2.5 Msps, up to 16 bits with hardware oversampling, conversion range up to 3.6 V Table 1. Device summary Reference Part number STM32WL55xx STM32WL55CC, STM32WL55JC, STM32WL55UC STM32WL54xx STM32WL54CC, STM32WL54JC, STM32WL54UC 2/147 DS13293 Rev 2