STR71xFxx STR710RZ ARM7TDMI 32-bit MCU with Flash, USB, CAN, 5 timers, ADC, 10 communication interfaces Features Core ARM7TDMI 32-bit RISC CPU LQFP64 10 x 10 59 MIPS 66 MHz from SRAM LQFP144 20 x 20 45 MIPS 50 MHz from Flash Memories Up to 256 Kbytes Flash program memory (10 kcycles endurance, 20 years retention 85 C) LFBGA64 LFBGA144 LFBGA64 8 x 8 x 1.7 8 x 8 x 1.7 10 x 10 x 1.7 16 Kbytes Flash data memory (100 kcycles endurance, 20 years retention 85 C) 5 timers Up to 64 Kbytes RAM 16-bit watchdog timer External Memory Interface (EMI) for up to 4 3 16-bit timers with 2 input captures, 2 banks of SRAM, Flash, ROM output compares, PWM and pulse counter Multi-boot capability 16-bit timer for timebase functions Clock, reset and supply management 10 communication interfaces 2 3.0 to 3.6 V application supply and I/Os 2 I C interfaces (1 multiplexed with SPI) Internal 1.8 V regulator for core supply 4 UART asynchronous serial interfaces Clock input from 0 to 16.5 MHz Smartcard ISO7816-3 interface on UART1 Embedded RTC osc. running from external 2 BSPI synchronous serial interfaces 32 kHz crystal CAN interface (2.0B Active) Embedded PLL for CPU clock USB Full Speed (12 Mbit/s) Device Realtime Clock for clock-calendar function Function with Suspend and Resume 5 power saving modes: SLOW, WAIT, HDLC synchronous communications LPWAIT, STOP and STANDBY modes 4-channel 12-bit A/D converter Nested interrupt controller Sampling frequency up to 1 kHz Fast interrupt handling with multiple vectors Conversion range: 0 to 2.5 V 32 vectors with 16 IRQ priority levels Development tools support 2 maskable FIQ sources Atomic bit SET and RES operations Up to 48 I/O ports 30/32/48 multifunctional bidirectional I/Os Table 1. Device summary Up to 14 ports with interrupt capability Reference Root part number STR710FZ1, STR710FZ2 STR711FR0, STR711FR1, STR711FR2, STR71xFxx STR712FR0, STR712FR1, STR712FR2, STR715FR0 STR710RZ STR710RZ April 2013 Doc ID 10350 Rev 13 1/80 www.st.com 1Contents STR71xFxx STR710RZ Contents 1 Introduction 6 2 Description . 7 3 System architecture . 8 3.1 On-chip peripherals 9 3.2 Related documentation 12 3.3 Pin description for 144-pin packages 13 3.4 Pin description for 64-pin packages . 23 3.5 External connections 29 3.6 I/O port configuration 30 3.7 Memory mapping . 31 4 Electrical parameters . 34 4.1 Parameter conditions 34 4.1.1 Minimum and maximum values . 34 4.1.2 Typical values . 34 4.1.3 Typical curves 34 4.1.4 Loading capacitor . 34 4.1.5 Pin input voltage 34 4.2 Absolute maximum ratings 35 4.3 Operating conditions 37 4.3.1 Supply current characteristics 38 4.3.2 Clock and timing characteristics 42 4.3.3 Memory characteristics . 47 4.3.4 EMC characteristics 48 4.3.5 I/O port pin characteristics . 51 4.3.6 TIM timer characteristics 56 4.3.7 EMI - external memory interface 56 4.3.8 I2C - inter IC control interface 60 4.3.9 BSPI - buffered serial peripheral interface . 63 4.3.10 USB characteristics 65 4.3.11 ADC characteristics 66 2/80 Doc ID 10350 Rev 13