STR91xFAxxx ARM966E-S 16/32-bit Flash MCU with Ethernet, USB, CAN, AC motor control, 4 timers, ADC, RTC, DMA Datasheet - production data Features 16/32-bit 96 MHz ARM9E based MCU ARM966E-S RISC core: Harvard archi- tecture, 5-stage pipeline, Tightly-Coupled LQFP80 12 x12mm LQFP128 14 x 14mm Memories (SRAM and Flash) STR91xFA implementation of core adds high-speed burst Flash memory interface, instruction prefetch queue, branch cache Up to 96 MIPS directly from Flash memory LFBGA144 10 x 10 mm Single-cycle DSP instructions supported Binary compatible with ARM7 code 3 16550-style UARTs with IrDA protocol Dual burst Flash memories, 32-bits wide 2 2 Fast I C, 400 kHz 256 KB/512 KB/1 MB/2 MB main Flash 2 channels for SPI, SSI, or 32 KB/128 KB secondary Flash MICROWIRE Sequential Burst operation up to 96 MHz External Memory Interface (EMI) 100 K min erase cycles, 20 yr min retention 8- or 16-bit data, up to 24-bit addressing SRAM, 32-bits wide Static Async modes for LQFP128 64K or 96K bytes, optional battery backup Additional burst synchronous modes for LFBGA144 9 programmable DMA channels Up to 80 I/O pins (muxed with interfaces) Clock, reset, and supply management 16-bit standard timers (TIM) Internal oscillator operating with external 4-25 MHz crystal 4 timers each with 2 input capture, 2 output compare, PWM and pulse count modes Internal PLL up to 96 MHz Real-time clock provides calendar 3-Phase induction motor controller (IMC) functions, tamper, and wake-up functions JTAG interface with boundary scan Reset Supervisor monitors supply voltage, watchdog, wake-up unit, external reset Embedded trace module (ARM ETM9) Brown-out monitor Run, Idle, and Sleep Mode as low as 50 uA Table 1. Device summary Vectored interrupt controller (VIC) Reference Part number 32 IRQ vectors, 30 interrupt pins STR910FAM32, STR910FAW32, Branch cache minimizes interrupt latency STR91xFAx32 STR910FAZ32, STR912FAW32 8-channel, 10-bit A/D converter (ADC) STR911FAM42, STR911FAW42, 0 to 3.6 V range, 0.7 usec conversion STR91xFAx42 STR912FAW42, STR912FAZ42 10 Communication interfaces STR911FAM44 STR911FAW44 10/100 Ethernet MAC with DMA and MII STR91xFAx44 STR912FAW44, STR912FAZ44 USB Full-speed (12 Mbps) slave device CAN interface (2.0B Active) STR911FAM46, STR911FAW46, STR91xFAx46 STR912FAW46, STR912FAZ46 STR911FAM47, STR911FAW47, STR91xFAx47 STR912FAW47, STR912FAZ47 March 2015 DocID13495 Rev 7 1/108 This is information on a product in full production. www.st.comContents STR91xFAxxx Contents 1 Description 10 2 Device summary . 11 3 Functional overview 12 3.1 System-in-a-package (SiP) . 12 3.2 Package choice 12 3.3 ARM966E-S CPU core . 12 3.4 Burst Flash memory interface . 12 3.4.1 Pre-fetch queue (PFQ) . 12 3.4.2 Branch cache (BC) 13 3.4.3 Management of literals . 13 3.5 SRAM (64 Kbytes or 96 Kbytes) . 15 3.5.1 Arbitration . 15 3.5.2 Battery backup 15 3.6 DMA data movement 15 3.7 Non-volatile memories . 16 3.7.1 Primary Flash memory 16 3.7.2 Secondary Flash memory . 16 3.8 One-time-programmable (OTP) memory . 17 3.8.1 Product ID and revision level . 17 3.9 Vectored interrupt controller (VIC) 18 3.9.1 FIQ handling . 18 3.9.2 IRQ handling . 18 3.9.3 Interrupt sources 18 3.10 Clock control unit (CCU) 20 3.10.1 Master clock sources . 20 3.10.2 Reference clock (RCLK) 21 3.10.3 AHB clock (HCLK) . 21 3.10.4 APB clock (PCLK) . 21 3.10.5 Flash memory interface clock (FMICLK) 22 3.10.6 UART and SSP clock (BRCLK) . 22 3.10.7 External memory interface bus clock (BCLK) 22 2/108 DocID13495 Rev 7