TS555IDT

TS555 Low-power single CMOS timer Datasheet - production data Description The TS555 is a single CMOS timer with very low consumption: SO8 (I TS555 = 110 A at V = +5 V versus cc(TYP) CC (a) (plastic micropackage) I NE555 = 3 mA), cc(TYP) and high frequency: (f TS555 = 2.7 MHz versus f(max.) Pin connections (a) f NE555 = 0.1 MHz). (max) (top view) Timing remains accurate in both monostable and astable mode. *1 9 && The TS555 provides reduced supply current ULJJHU 7 LVFKDUJH spikes during output transitions, which enable the W 2XWSX 7KUHVKROG use of lower decoupling capacitors compared to &RQWURO 5HVHW (a) those required by bipolar NE555 . ROWDJH 9 12 With the high input impedance (10 ), timing capacitors can also be minimized. Features Very low power consumption: 110 A typ at V = 5 V CC 90 a typ at V = 3 V CC High maximum astable frequency of 2.7 MHz Pin-to-pin functionally-compatible with bipolar (a) NE555 Wide voltage range: +2 V to +16 V Supply current spikes reduced during output transitions 12 High input impedance: 10 Output compatible with TTL, CMOS and logic MOS a. Terminated product June 2015 DocID4077 Rev 4 1/19 This is information on a product in full production. www.st.comContents TS555 Contents 1 Absolute maximum ratings and operating conditions . 3 2 Schematic diagrams . 4 3 Electrical characteristics . 6 4 Application information . 13 4.1 Monostable operation 13 4.2 Astable operation . 14 5 Package information 15 5.1 SO8 package information . 16 6 Ordering information . 17 7 Revision history . 18 2/19 DocID4077 Rev 4