VIPER100ASPTR-E STMicroelectronics

VIPer100A-E VIPer100ASP-E SMPS PRIMARY I.C. General Features V I R Type DSS n DS(on) 10 VIPer100A-E/ASP-E 700V 3 A 2.8 1 TM POWERSO-10 ADJUSTABLE SWITCHING FREQUENCY UP PENTAWATT HV TO 200 kHz PENTAWATT HV (022Y) CURRENT MODE CONTROL SOFT START AND SHUTDOWN CONTROL AUTOMATIC BURST MODE OPERATION IN Description STAND-BY CONDITION ABLE TO MEET BLUE ANGEL NORM (<1w TOTAL POWER VIPer100A-E/ASP-E, made using VIPower M0 CONSUMPTION) Technology, combines on the same silicon chip a state-of-the-art PWM circuit together with an INTERNALLY TRIMMED ZENER optimized, high voltage, Vertical Power MOSFET REFERENCE (700V/ 3A). UNDERVOLTAGE LOCK-OUT WITH Typical applications cover offline power supplies HYSTERESIS with a secondary power capability of 50W in wide INTEGRATED START-UP SUPPLY range condition and 100W in single range or with OVER-TEMPERATURE PROTECTION doubler configuration. It is compatible from both primary or secondary regulation loop despite LOW STAND-BY CURRENT using around 50% less components when ADJUSTABLE CURRENT LIMITATION compared with a discrete solution. Burst mode operation is an additional feature of this device, offering the ability to operate in stand-by mode Block Diagram without extra components. OSC DRAIN ON/OFF OSCILLATOR SECURITY PWM LATCH LATCH S FF UVLO VDD R/S Q R1 Q FF LOGIC S R2 R3 OVERTEMP. DETECTOR 0.5V + 0.5 V + + 1.7 s 1 V/A 250 ns DELAY BLANKING CURRENT ERROR AMPLIFIER AMPLIFIER 13 V + 4.5 V COMP SOURCE Rev 1 September 2005 1/31 www.st.com 31 FC00231 VIPer100A-E/ASP-E Contents 1 Electrical Data 4 1.1 Maximum Rating . 4 1.2 Electrical Characteristics . 5 2 Thermal Data . 7 3 Pin Description . 8 3.1 Drain Pin (Integrated Power MOSFET Drain): 8 3.2 Source Pin: . 8 3.3 V Pin (Power Supply): . 8 DD 3.4 Compensation Pin 8 3.5 OSC Pin (Oscillator Frequency): . 9 4 Typical Circuit . 10 5 Operation Description . 11 5.1 Current Mode Topology: .11 5.2 Stand-by Mode 11 5.3 High Voltage Start-up Current Suorce 12 5.4 Transconductance Error Amplifier . 13 5.5 External Clock Synchronization: 14 5.6 Primary Peak Current Limitation 14 5.7 Over-Temperature Protection 14 5.8 Operation Pictures 15 2/31