DESCRIPTION www.epc-co.com Contact us: Development Board EPC9004 The EPC9004 development board is a 200 V maximum device volt- Texas Instruments UCC27611 gate drivers as well as supply and www.epc-co.com age, 2 A maximum output current, half bridge with onboard gate bypass capacitors. The board contains all critical components and Quick Start Guide Renee Yawger Bhasy Nair drives, featuring the EPC2012 enhancement mode (eGaN) field layout for optimal switching performance. There are also various WW Marketing Global FAE Support effect transistor (FET). The purpose of this development board is probe points to facilitate simple waveform measurement and ef- Office: +1.908.475.5702 Office: +1.972.805.8585 to simplify the evaluation process of the EPC2012 eGaN FET by in- ficiency calculation. A complete block diagram of the circuit is 200 V Half-Bridge with Gate Drive, Using EPC2012 Mobile: +1.908.619.9678 Mobile: +1.469.879.2424 cluding all the critical components on a single board that can be given in Figure 1. renee.yawger epc-co.com bhasy.nair epc-co.com easily connected into any existing converter. Stephen Tsang Peter Cheng For more information on the EPC2012 eGaN FET please refer to the Sales, Asia FAE Support, Asia The EPC9004 development board is 2 x 1.5 and contains not only datasheet available from EPC at www.epc-co.com. The datasheet Mobile: +852.9408.8351 Mobile: +886.938.009.706 two EPC2012 eGaN FET in a half bridge configuration using two should be read in conjunction with this quick start guide. stephen.tsang epc-co.com peter.cheng epc-co.com Table 1: Performance Summary (TA = 25C) SYMBOL PARAMETER CONDITIONS MIN MAX UNITS V Gate Drive Input Supply Range 712V DD V Bus Input Voltage Range 150 V IN V Switch Node Output Voltage 200 V OUT EPC Products are distributed exclusively through Digi-Key. I Switch Node Output Current 2* A OUT www.digikey.com Input High 3.5 6V V PWM Logic Input Voltage Threshold PWM Development Board / Demonstration Board Notification Input Low0 1.5 V The EPC9004 board is intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations. Minimum High State Input Pulse Width VPWM rise and fall time < 10ns 100 ns As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are not RoHS compliant. Efficient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant. Minimum Low State Input Pulse Width VPWM rise and fall time < 10ns 500 ns No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind. * Assumes inductive load, maximum current depends on die temperature actual maximum current with be subject to switching frequency, bus voltage and thermals. EPC reserves the right at any time, without notice, to change said circuitry and specifications. Dependent on time needed to refresh high side bootstrap supply voltage. 7 V 12 V EPC9004, 200V DEVELOPMENT BOARD Quick Start Procedure V Gate Drive Rev. 1.0 DD eGaN FET Gate Drive Half-Bridge with Bypass Supply V Supply DD EPC 2011 Regulator + V IN Development board EPC9004 is easy to set up to evaluate the performance of the EPC1012 eGaN FET. Refer to Figure 2 for proper connect Gate Drive Supply (Note Polarity) and measurement setup and follow the procedure below: A PWM Enable Level Shift, Input OUT I IN 1. With power off, connect the input power supply bus to +VIN (J5, J6) and ground / return to VIN (J7, J8). < + 150 V + Dead-time Adjust Switch Node V VIN Supply 2. With power off, connect the switch node of the half bridge OUT (J3, J4) to your circuit as required. and Gate Drive IN V 3. With power off, connect the gate drive input to +VDD (J1, Pin-1) and ground return to VDD (J1, Pin-2). (For E ciency External Circuit Measurement) 4. With power off, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins. 5. Turn on the gate drive supply make sure the supply is between 7 V and 12 V range. PWM Input 6. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage of 200 V on V ). OUT Figure 1: Block Diagram of EPC9004 Development Board 7. Turn on the controller / PWM input source and probe switching node to see switching operation. EPC EFFICIENT POWER CONVERSION 8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior, efficiency and other parameters. Figure 2: Proper Connection and Measurement Setup 9. For shutdown, please follow steps in reverse. EPC9004, 200V DEVELOPMENT BOARD NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the Rev. 1.0 eGaN FET EPC 2011 Do not use probe ground lead oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See Figure 3 for proper scope probe technique. THERMAL CONSIDERATIONS Ground probe The EPC9004 development board showcases the EPC1012 eGaN FET. Although the electrical performance surpasses that for traditional Si devices, against TP3 their relatively smaller size does magnify the thermal management requirements. The EPC9004 is intended for bench evaluation with low ambi- ent temperature and convection cooling. The addition of heat-sinking and forced air cooling can significantly increase the current rating of these devices, but care must be taken to not exceed the absolute maximum die temperature of 125C. EPC EFFICIENT POWER CONVERSION Minimize loop Place probe in large via at OUT Figure 4: Waveforms for VIN = 150 V to 5 V/2 A (100kHz) Buck converter NOTE. The EPC9004 development board does not have any current or thermal protection on board. CH1: VPWM Input voltage CH2: (IOUT) Switch node current CH4: (VOUT) Switch node voltage Figure 3: Proper Measurement of Switch Node OUTDESCRIPTION www.epc-co.com Contact us: Development Board EPC9004 The EPC9004 development board is a 200 V maximum device volt- Texas Instruments UCC27611 gate drivers as well as supply and www.epc-co.com age, 2 A maximum output current, half bridge with onboard gate bypass capacitors. The board contains all critical components and Quick Start Guide Renee Yawger Bhasy Nair drives, featuring the EPC2012 enhancement mode (eGaN) field layout for optimal switching performance. There are also various WW Marketing Global FAE Support effect transistor (FET). The purpose of this development board is probe points to facilitate simple waveform measurement and ef- Office: +1.908.475.5702 Office: +1.972.805.8585 to simplify the evaluation process of the EPC2012 eGaN FET by in- ficiency calculation. A complete block diagram of the circuit is 200 V Half-Bridge with Gate Drive, Using EPC2012 Mobile: +1.908.619.9678 Mobile: +1.469.879.2424 cluding all the critical components on a single board that can be given in Figure 1. renee.yawger epc-co.com bhasy.nair epc-co.com easily connected into any existing converter. Stephen Tsang Peter Cheng For more information on the EPC2012 eGaN FET please refer to the Sales, Asia FAE Support, Asia The EPC9004 development board is 2 x 1.5 and contains not only datasheet available from EPC at www.epc-co.com. The datasheet Mobile: +852.9408.8351 Mobile: +886.938.009.706 two EPC2012 eGaN FET in a half bridge configuration using two should be read in conjunction with this quick start guide. stephen.tsang epc-co.com peter.cheng epc-co.com Table 1: Performance Summary (TA = 25C) SYMBOL PARAMETER CONDITIONS MIN MAX UNITS V Gate Drive Input Supply Range 712V DD V Bus Input Voltage Range 150 V IN V Switch Node Output Voltage 200 V OUT EPC Products are distributed exclusively through Digi-Key. I Switch Node Output Current 2* A OUT www.digikey.com Input High 3.5 6V V PWM Logic Input Voltage Threshold PWM Development Board / Demonstration Board Notification Input Low0 1.5 V The EPC9004 board is intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations. Minimum High State Input Pulse Width VPWM rise and fall time < 10ns 100 ns As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are not RoHS compliant. Efficient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant. Minimum Low State Input Pulse Width VPWM rise and fall time < 10ns 500 ns No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind. * Assumes inductive load, maximum current depends on die temperature actual maximum current with be subject to switching frequency, bus voltage and thermals. EPC reserves the right at any time, without notice, to change said circuitry and specifications. Dependent on time needed to refresh high side bootstrap supply voltage. 7 V 12 V EPC9004, 200V DEVELOPMENT BOARD Quick Start Procedure V Gate Drive Rev. 1.0 DD eGaN FET Gate Drive Half-Bridge with Bypass Supply V Supply DD EPC 2011 Regulator + V IN Development board EPC9004 is easy to set up to evaluate the performance of the EPC1012 eGaN FET. Refer to Figure 2 for proper connect Gate Drive Supply (Note Polarity) and measurement setup and follow the procedure below: A PWM Enable Level Shift, Input OUT I IN 1. With power off, connect the input power supply bus to +VIN (J5, J6) and ground / return to VIN (J7, J8). < + 150 V + Dead-time Adjust Switch Node V VIN Supply 2. With power off, connect the switch node of the half bridge OUT (J3, J4) to your circuit as required. and Gate Drive IN V 3. With power off, connect the gate drive input to +VDD (J1, Pin-1) and ground return to VDD (J1, Pin-2). (For E ciency External Circuit Measurement) 4. With power off, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins. 5. Turn on the gate drive supply make sure the supply is between 7 V and 12 V range. PWM Input 6. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage of 200 V on V ). OUT Figure 1: Block Diagram of EPC9004 Development Board 7. Turn on the controller / PWM input source and probe switching node to see switching operation. EPC EFFICIENT POWER CONVERSION 8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior, efficiency and other parameters. Figure 2: Proper Connection and Measurement Setup 9. For shutdown, please follow steps in reverse. EPC9004, 200V DEVELOPMENT BOARD NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the Rev. 1.0 eGaN FET EPC 2011 Do not use probe ground lead oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See Figure 3 for proper scope probe technique. THERMAL CONSIDERATIONS Ground probe The EPC9004 development board showcases the EPC1012 eGaN FET. Although the electrical performance surpasses that for traditional Si devices, against TP3 their relatively smaller size does magnify the thermal management requirements. The EPC9004 is intended for bench evaluation with low ambi- ent temperature and convection cooling. The addition of heat-sinking and forced air cooling can significantly increase the current rating of these devices, but care must be taken to not exceed the absolute maximum die temperature of 125C. EPC EFFICIENT POWER CONVERSION Minimize loop Place probe in large via at OUT Figure 4: Waveforms for VIN = 150 V to 5 V/2 A (100kHz) Buck converter NOTE. The EPC9004 development board does not have any current or thermal protection on board. CH1: VPWM Input voltage CH2: (IOUT) Switch node current CH4: (VOUT) Switch node voltage Figure 3: Proper Measurement of Switch Node OUT