DESCRIPTION www.epc-co.com Contact us: Development Board EPC9006 The EPC9006 development board is a 100 V maximum device volt- National LM5113 gate driver, supply and bypass capacitors. The www.epc-co.com age, 5 A maximum output current, half bridge with onboard gate board contains all critical components and layout for optimal Quick Start Guide Renee Yawger Bhasy Nair drives, featuring the EPC2007 enhancement mode (eGaN) field switching performance. There are also various probe points to fa- WW Marketing Global FAE Support effect transistor (FET). The purpose of this development board is cilitate simple waveform measurement and efficiency calculation. Office: +1.908.475.5702 Office: +1.972.805.8585 100 V Half-Bridge with Gate Drive, Using EPC2007 to simplify the evaluation process of the EPC2007 eGaN FET by A complete block diagram of the circuit is given in Figure 1. Mobile: +1.908.619.9678 Mobile: +1.469.879.2424 including all the critical components on a single board that can be renee.yawger epc-co.com bhasy.nair epc-co.com easily connected into any existing converter. For more information on the EPC2007s eGaN FET please refer to Stephen Tsang Peter Cheng the datasheet available from EPC at www.epc-co.com. The data- Sales, Asia FAE Support, Asia The EPC9006 development board is 2 x 1.5 and contains not sheet should be read in conjunction with this quick start guide. Mobile: +852.9408.8351 Mobile: +886.938.009.706 only two EPC2007 eGaN FET in a half bridge configuration using stephen.tsang epc-co.com peter.cheng epc-co.com Table 1 Performance Summary (T = 25C) A SYMBOL PARAMETER CONDITIONS MIN MAX UNITS V Gate Drive Input Supply Range 7 12 V DD V Bus Input Voltage Range 70* V IN V Switch Node Output Voltage 100 V OUT EPC Products are distributed exclusively through Digi-Key. I Switch Node Output Current 5* A OUT www.digikey.com V PWM Logic Input Voltage Threshold Input High 3.5 6 V PWM Development Board / Demonstration Board Notification Input Low 0 1.5 V The EPC9006 board is intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations. Minimum High State Input Pulse Width V rise and fall time < 10ns 30 ns PWM As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are not RoHS compliant. Efficient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant. Minimum Low State Input Pulse Width V rise and fall time < 10ns 100 ns PWM No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind. *Assumes inductive load, maximum current depends on die temperature actual maximum current with be subject to switching frequency, bus voltage and thermals. EPC reserves the right at any time, without notice, to change said circuitry and specifications. Limited by time needed to refresh high side bootstrap supply voltage. 7 V 12 V 6, 100 Quick Start Procedure Gate Drive V DD Gate Drive VDD Supply Supply Half-Bridge with Bypass + Regulator V IN Gate Drive Supply Development board EPC9006 is easy to set up to evaluate the performance of the EPC2007 eGaN FET. Refer to Figure 2 for proper connect (Note Polarity) A and measurement setup and follow the procedure below: Logic and PWM LM5113 I IN OUT Input Dead-time < + 70 V Gate 1. With power off, connect the input power supply bus to +VIN (J5,J6) and ground / return to VIN (J7,J8). + Adjust Switch Node Driver VIN Supply VIN V 2. With power off, connect the switch node of the half bridge OUT (J3,J4) to your circuit as required. (For E ciency 3. With power off, connect the gate drive input to +VDD (J1, Pin-1) and ground return to VDD (J1, Pin-2). External Circuit Measurement) 4. With power off, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins. 5. Turn on the gate drive supply make sure the supply is between 7 V and 12 V range. PWM Input Figure 1: Block Diagram of EPC9006 Development Board 6. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage of 100 V on VOUT). EPC 7. Turn on the controller / PWM input source and probe switching node to see switching operation. EFFICIENT POWER CONVERSION 8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior, Figure 2: Proper Connection and Measurement Setup efficiency and other parameters. 9. For shutdown, please follow steps in reverse. 6, 100 NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the Do not use probe ground lead oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See Figure 3 for proper scope probe technique. Do not let the probe tip touch the low-side die. Do not let probe tip touch back of low-side die THERMAL CONSIDERATIONS Ground probe against TP3 The EPC9006 development board showcases the EPC2007 eGaN FET. Although the electrical performance surpasses that for traditional Si devices, their relatively smaller size does magnify the thermal management requirements. The EPC9006 is intended for bench evaluation with low ambi- ent temperature and convection cooling. The addition of heat-sinking and forced air cooling can significantly increase the current rating of these EPC devices, but care must be taken to not exceed the absolute maximum die temperature of 125C. EFFICIENT POWER CONVERSION Minimize loop Place probe in large via at OUT Figure 4: Typical Waveforms for VIN = 48 V to 5 V/5 A (1000kHz) Buck converter CH1: VPWM Input voltage CH2: (IOUT) Switch node current CH4: (VOUT) Switch node voltage Figure 3: Proper Measurement of Switch Node OUT NOTE. The EPC9006 development board does not have any current or thermal protection on board. DESCRIPTION www.epc-co.com Contact us: Development Board EPC9006 The EPC9006 development board is a 100 V maximum device volt- National LM5113 gate driver, supply and bypass capacitors. The www.epc-co.com age, 5 A maximum output current, half bridge with onboard gate board contains all critical components and layout for optimal Quick Start Guide Renee Yawger Bhasy Nair drives, featuring the EPC2007 enhancement mode (eGaN) field switching performance. There are also various probe points to fa- WW Marketing Global FAE Support effect transistor (FET). The purpose of this development board is cilitate simple waveform measurement and efficiency calculation. Office: +1.908.475.5702 Office: +1.972.805.8585 100 V Half-Bridge with Gate Drive, Using EPC2007 to simplify the evaluation process of the EPC2007 eGaN FET by A complete block diagram of the circuit is given in Figure 1. Mobile: +1.908.619.9678 Mobile: +1.469.879.2424 including all the critical components on a single board that can be renee.yawger epc-co.com bhasy.nair epc-co.com easily connected into any existing converter. For more information on the EPC2007s eGaN FET please refer to Stephen Tsang Peter Cheng the datasheet available from EPC at www.epc-co.com. The data- Sales, Asia FAE Support, Asia The EPC9006 development board is 2 x 1.5 and contains not sheet should be read in conjunction with this quick start guide. Mobile: +852.9408.8351 Mobile: +886.938.009.706 only two EPC2007 eGaN FET in a half bridge configuration using stephen.tsang epc-co.com peter.cheng epc-co.com Table 1 Performance Summary (T = 25C) A SYMBOL PARAMETER CONDITIONS MIN MAX UNITS V Gate Drive Input Supply Range 7 12 V DD V Bus Input Voltage Range 70* V IN V Switch Node Output Voltage 100 V OUT EPC Products are distributed exclusively through Digi-Key. I Switch Node Output Current 5* A OUT www.digikey.com V PWM Logic Input Voltage Threshold Input High 3.5 6 V PWM Development Board / Demonstration Board Notification Input Low 0 1.5 V The EPC9006 board is intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations. Minimum High State Input Pulse Width V rise and fall time < 10ns 30 ns PWM As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are not RoHS compliant. Efficient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant. Minimum Low State Input Pulse Width V rise and fall time < 10ns 100 ns PWM No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind. *Assumes inductive load, maximum current depends on die temperature actual maximum current with be subject to switching frequency, bus voltage and thermals. EPC reserves the right at any time, without notice, to change said circuitry and specifications. Limited by time needed to refresh high side bootstrap supply voltage. 7 V 12 V 6, 100 Quick Start Procedure Gate Drive V DD Gate Drive VDD Supply Supply Half-Bridge with Bypass + Regulator V IN Gate Drive Supply Development board EPC9006 is easy to set up to evaluate the performance of the EPC2007 eGaN FET. Refer to Figure 2 for proper connect (Note Polarity) A and measurement setup and follow the procedure below: Logic and PWM LM5113 I IN OUT Input Dead-time < + 70 V Gate 1. With power off, connect the input power supply bus to +VIN (J5,J6) and ground / return to VIN (J7,J8). + Adjust Switch Node Driver VIN Supply VIN V 2. With power off, connect the switch node of the half bridge OUT (J3,J4) to your circuit as required. (For E ciency 3. With power off, connect the gate drive input to +VDD (J1, Pin-1) and ground return to VDD (J1, Pin-2). External Circuit Measurement) 4. With power off, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins. 5. Turn on the gate drive supply make sure the supply is between 7 V and 12 V range. PWM Input Figure 1: Block Diagram of EPC9006 Development Board 6. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage of 100 V on VOUT). EPC 7. Turn on the controller / PWM input source and probe switching node to see switching operation. EFFICIENT POWER CONVERSION 8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior, Figure 2: Proper Connection and Measurement Setup efficiency and other parameters. 9. For shutdown, please follow steps in reverse. 6, 100 NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the Do not use probe ground lead oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See Figure 3 for proper scope probe technique. Do not let the probe tip touch the low-side die. Do not let probe tip touch back of low-side die THERMAL CONSIDERATIONS Ground probe against TP3 The EPC9006 development board showcases the EPC2007 eGaN FET. Although the electrical performance surpasses that for traditional Si devices, their relatively smaller size does magnify the thermal management requirements. The EPC9006 is intended for bench evaluation with low ambi- ent temperature and convection cooling. The addition of heat-sinking and forced air cooling can significantly increase the current rating of these EPC devices, but care must be taken to not exceed the absolute maximum die temperature of 125C. EFFICIENT POWER CONVERSION Minimize loop Place probe in large via at OUT Figure 4: Typical Waveforms for VIN = 48 V to 5 V/5 A (1000kHz) Buck converter CH1: VPWM Input voltage CH2: (IOUT) Switch node current CH4: (VOUT) Switch node voltage Figure 3: Proper Measurement of Switch Node OUT NOTE. The EPC9006 development board does not have any current or thermal protection on board.