MUX DAC1 DAC0 DATASHEET FOUR CHANNEL HD AUDIO CODEC 92HD95 OPTIMIZED FOR LOW POWER/LOW COST DESCRIPTION SOFTWARE SUPPORT The 92HD95 is a low power optimized, high fidelity, Intuitive TSI HD Sound graphical user interface 4-channel audio codec compatible with Intels High Defini- that allows configurability and preference settings tion (HD) Audio Interface. The 92HD95 provides high qual- Output Path Processing ity, HD Audio capability to notebook and desktop PC 12 band fully parametric equalizer applications. Compressor/limiter allows higher average volume level without resonances or damage to speakers. FEATURES Enables improved voice articulation Constant, system-level effects tuned to optimize a 4 Channel (2 stereo DACs, 2 stereo ADCs) with particular platform can be combined with user-mode 24-bit resolution presets tailored for specific acoustical environments and applications Microsoft WLP premium logo compliant System-level effects automatically disabled when 3W(4ohm)/1.5W(8ohm) Class-D Stereo BTL external audio connections made Amplifier Input Path Processing Selectable frequency hardware high-pass filter for 2 band fully parametric equalizer to allow for shaping of speaker protection. microphone response 10 band hardware parametric equalizer (5 bands per Compressor/limiter allows higher average volume level channel) for speaker optimization in ALL operating Available near-field and far-field voice capture scenarios algorithms to support conference room/lecture hall Hardware compressor limiter allows higher average applications volume level without resonances or damage to Microphone Beam Forming, Acoustic Echo speakers. Cancellation, and Noise Suppression Integrated Class-G true capless stereo headphone TSI APO wrapper amplifier with charge pump/LDO Enables multiple APOs to be used with the TSI Driver 4 analog ports with port presence detect (3 single Dynamic Stream Switching ended, 1 BTL) Improved multi-streaming (Real Time Communication) Combo Jack Support allowing for dual-function user experience with less support calls headphone and headset detection Broad 3rd party branded software including 2 Voltage adjustable VREF Out pins for Creative, Dolby, DTS, Waves, Sonic Focus & SRS microphone bias 2 Digital microphone inputs (4 mic support) Microphone Mute Input Selectable 1.5V and 3.3V HDA signaling 40 39 38 37 36 35 34 33 32 31 Internal DVDD LDO voltage regulator DVDD CORE 1 30 AVDD2 BTL BTL Supports Runtime D3 (RTD3) low power mode DMIC CLK/GPIO 1 2 29 CPVreg Digital PWM controller Digital Mic DMIC 0/GPIO 2 3 28 FCap1 Capable of MSLync Compliance Interface Stereo 5-band EQ Highpass Filter DMIC 1/GPIO 0 4 27 FCap2 Full HDA015-B and EuP low power support Stereo MUX SDATA OUT 5 DAC0 26 VNeg Audio inactivity transitions codec from D0 to D3 low DAC 0 power mode Stereo BITCLK 6 25 VPos DAC1 DAC 1 Resume from D3 to D0 with audio activity in < 10 msec DMIC0 7 HP 24 DVDDIO PORTA R DMIC1 Stereo DAC0 DAC0 D3 to D0 transition with < -65dB pop/click ADC0 DAC1 DAC1 8 HP 23 SDATA IN PORTA L Port presence detect in D3 with or without bit clock DMIC0 DMIC1 Stereo PC beep wake up in D3 9 DAC0 22 DVDD AVDD1 ADC1 DAC1 MUX Additional vendor specific modes for even lower power 10 21 SYNC CAP2 3.3 V analog power supply 11 12 13 14 15 16 17 18 19 20 Digital and Analog PC Beep to all outputs 40-pin 5mm x 5mm QFN RoHS package 1 V 1.4 01/17 2017 TEMPO SEMICONDCUTOR, INC. 92HD95 RESET HD Audio Interface SPDIF/GPIO3 PC Beep EAPD SENSE A PVDD MUX MUX PORTC L PORTD +R PORTC R PORTD -R VrefOut C PVSS PORTB L PVSS PORTB R PORTD -L VrefOut B PORTD +L VrefFilt Charge-Pump PVDD92HD95 SINGLE CHIP PC AUDIO SYSTEM,CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO TABLE OF CONTENTS 1. DESCRIPTION .......................................................................................................................... 9 1.1. Overview ............................................................................................................................................9 1.2. Orderable Part Numbers ....................................................................................................................9 2. DETAILED DESCRIPTION ..................................................................................................... 10 2.1. Port Functionality .............................................................................................................................10 2.1.1. Port Characteristics ............................................................................................................10 2.1.2. Vref Out .............................................................................................................................11 2.1.3. Jack Detect ........................................................................................................................12 2.1.4. SPDIF Output .....................................................................................................................12 2.2. ADC Multiplexers .............................................................................................................................13 2.3. Power Management .........................................................................................................................13 2.4. AFG D0 ............................................................................................................................................14 2.5. AFG D1 ............................................................................................................................................14 2.6. AFG D2 ............................................................................................................................................15 2.7. AFG D3 ............................................................................................................................................15 2.7.1. AFG D3cold / RTD3 ...........................................................................................................15 2.8. Vendor Specific Function Group Power States D4/D5 ....................................................................15 2.9. 4.12 Vendor Specific Function Group Power State D5 Kill ............................................................16 2.10. Low-voltage HDA Signaling ...........................................................................................................16 2.11. Multi-channel capture ....................................................................................................................16 2.12. EAPD .............................................................................................................................................18 2.13. Digital Microphone Support ...........................................................................................................21 2.14. Analog PC-Beep ............................................................................................................................25 2.15. Digital PC-Beep .............................................................................................................................27 2.16. Headphone Drivers ........................................................................................................................28 2.17. Class-D BTL Amplifier ....................................................................................................................28 2.18. BTL Amplifier High-Pass Filter .......................................................................................................28 2.18.1. Filter Description ..............................................................................................................29 2.19. EQ ..................................................................................................................................................29 2.20. Combo Jack Detection ...................................................................................................................29 2.21. GPIO ..............................................................................................................................................30 2.21.1. GPIO Pin mapping and shared functions .........................................................................30 2.21.2. SPDIF/GPIO Selection .....................................................................................................30 2.21.3. Digital Microphone/GPIO Selection .................................................................................30 2.22. HD Audio HDA015-B support ........................................................................................................30 2.23. Digital Core Voltage Regulator ......................................................................................................31 2.24. Microphone Mute Input ..................................................................................................................31 3. CHARACTERISTICS ............................................................................................................... 32 3.1. Electrical Specifications ...................................................................................................................32 3.1.1. Absolute Maximum Ratings ...............................................................................................32 3.1.2. Recommended Operating Conditions ................................................................................32 3.2. 92HD95 Analog Performance Characteristics .................................................................................33 3.3. Class-D BTL Amplifier Performance ................................................................................................36 3.4. Capless Headphone Supply Characteristics ....................................................................................37 3.5. AC Timing Specs .............................................................................................................................37 3.5.1. HD Audio Bus Timing .........................................................................................................37 3.5.2. SPDIF Timing .....................................................................................................................38 3.5.3. Digital Microphone Timing .................................................................................................38 3.5.4. GPIO Characteristics .........................................................................................................38 4. FUNCTIONAL BLOCK DIAGRAM .......................................................................................... 39 5. WIDGET DIAGRAM ................................................................................................................ 40 6. PORT AND PIN CONFIGURATIONS ..................................................................................... 41 6.1. Port Configurations ..........................................................................................................................41 6.2. Pin Configuration Default Register Settings .....................................................................................42 7. WIDGET INFORMATION ........................................................................................................ 43 7.1. Widget List .......................................................................................................................................44 7.2. Reset Key ........................................................................................................................................45 2 V 1.4 01/17 2017 TEMPO SEMICONDCUTOR, INC. 92HD95