STAC9200X5TAEB1X Tempo Semiconductor

DATA SHEET 2- CHANNEL HIGH DEFINITION AUDIO CODEC STAC9200 Sample rates up to 192 KHz Description Mixer-less design The STAC9200 is a high quality, 2-channel audio CODEC Low-latency Karaoke Mode Supported compatible with the Intel High Definition (HD) Audio Integrated Headphone Amplifiers Interface. The STAC9200 provides Stereo 24-Bit resolution with sample rates up to 192 KHz. SPDIF I/O provides Stereo Microphone connectivity to consumer electronic equipment. The Supports Stereo Microphone STAC9200 incorporates TSI s proprietary SD technology to Microphone Boost 0, 10, 20, 30, 40dB achieve an estimated DAC SNR in excess of 100dB. The Direct CDROM Recording Mixerless Design STAC9200 provides high quality, HD Audio capability to notebook and cost sensitive desktop PC applications. S/PDIF In and Out TM Universal Jacks Functionality for jack retasking Features Adjustable VREF Out High performance SD technology Digital PC Beep to all outputs 100dB DAC SNR +3.3 V, +4 V and +5 V analog power supply options (The +4 V Analog voltage is supported by the +5 V version of Intel HD Audio Interface the STAC9200. Request +4 V configuration of the driver.) Two Channel DACs and ADCs with 24-bit 32-pad QFN (5mm x 5mm) and 48-pin LQFP resolution package options TSI CONFIDENTIAL 1 V 1.8 10/14 2014 TEMPO SEMICONDCUTOR, INC. STAC9200STAC9200 2-Channel High Definition Audio Codec Table of Contents 1. DESCRIPTION ........................................................................................................................ 11 2. PERFORMANCE ..................................................................................................................... 12 2.1. Audio Fidelity ...................................................................................................................................12 2.2. Electrical Specifications ...................................................................................................................12 2.2.1. Absolute Maximum Ratings ...............................................................................................12 2.2.2. Recommended Operation Conditions ................................................................................12 2.3. Power Consumption ........................................................................................................................13 2.3.1. Digital .................................................................................................................................13 2.3.2. Analog ................................................................................................................................13 2.4. STAC9200 5V Analog Performance Characteristics .......................................................................14 2.5. STAC9200 4V Analog Performance Characteristics .......................................................................16 2.6. STAC9200 3.3V Analog Performance Characteristics ....................................................................18 3. EXTENDED FEATURE EXPLANATION ................................................................................. 20 3.1. SPDIF Input .....................................................................................................................................20 3.2. SPDIF Output ..................................................................................................................................20 3.3. Universal JacksTM ...........................................................................................................................20 3.4. Audio Jack Presence Detect ............................................................................................................20 4. BLOCK DIAGRAMS AND TYPICAL HOOKUPS ................................................................... 21 4.1. Functional Block Diagram ................................................................................................................21 4.2. STAC9200 Typical Connection Diagram for 48-pin LQFP ...............................................................22 4.3. STAC9200 Split Independent Power Supply for 48-pin LQFP .........................................................22 4.4. STAC9200 Typical Connection Diagram for 32-pad QFN ...............................................................22 4.5. STAC9200 Split Independent Power Supply for 32-pad QFN .........................................................22 5. WIDGET INFORMATION ........................................................................................................ 23 5.1. Widget Diagram ...............................................................................................................................23 5.2. STAC9200 Widget List ....................................................................................................................24 5.3. Root Node (NID = 0x00) ..................................................................................................................25 5.3.1. Root PnpID .......................................................................................................................25 5.3.2. Root RevID .....................................................................................................................25 5.3.3. Root NodeInfo ...................................................................................................................26 5.4. AFG Node (NID = 0x01) ..................................................................................................................26 5.4.1. AFG Reset ........................................................................................................................26 5.4.2. AFG NodeInfo ...................................................................................................................27 5.4.3. AFG Type ..........................................................................................................................27 5.4.4. AFG GrpCap .....................................................................................................................27 5.4.5. AFG FrmtCap ....................................................................................................................28 5.4.6. AFG StreamCap ...............................................................................................................29 5.4.7. AFG PwrCap .....................................................................................................................30 5.4.8. AFG GPIOCap ..................................................................................................................30 5.4.9. AFG OutAmpCap ..............................................................................................................31 5.4.10. AFG PwrState .................................................................................................................32 5.4.11. AFG UnsolResp ..............................................................................................................32 5.4.12. AFG GPIO .......................................................................................................................33 5.4.13. AFG GPIOEn ..................................................................................................................34 5.4.14. AFG GPIODir ..................................................................................................................35 5.4.15. AFG GPIOWake .............................................................................................................35 5.4.16. AFG GPIOUnsolEn .........................................................................................................36 5.4.17. AFG GPIOSticky .............................................................................................................37 5.4.18. AFG SysID ......................................................................................................................38 5.5. DAC0Cnvtr Node (NID = 0x02) ........................................................................................................39 5.5.1. DAC0Cnvtr Frmt ...............................................................................................................39 5.5.2. DAC0Cnvtr WCap .............................................................................................................40 5.5.3. DAC0Cnvtr PwrState .........................................................................................................41 5.5.4. DAC0Cnvtr Stream ...........................................................................................................42 5.6. ADC0Cnvtr Node (NID = 0x03) .......................................................................................................42 5.6.1. ADC0Cnvtr Frmt ...............................................................................................................42 5.6.2. ADC0Cnvtr WCap .............................................................................................................43 TSI CONFIDENTIAL 2 V 1.8 10/14 2014 TEMPO SEMICONDCUTOR, INC. STAC9200