DATASHEET TWO-CHANNEL, 20-BIT, AC97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING STAC9752/9753 20-bit full duplex stereo ADCs, DACs Description Independent sample rates for ADCs & DACs TSI s STAC9752/9753 are general purpose 20-bit, full 5-wire AC-Link protocol compliance duplex, audio CODECs conforming to the analog 20-bit SPDIF Output component specification of AC 97 (Audio CODEC 97 Component Specification Rev. 2.3). The STAC9752/9753 Internal Jack Sensing on Headphone and Line Out incorporate TSI s proprietary SD technology to achieve a Internal Microphone Input Sensing DAC SNR in excess of 90dB. The DACs, ADCs and mixer Digital PC Beep Option are integrated with analog I/Os, which include four analog line-level stereo inputs, two analog line-level mono inputs, Extended AC97 2.3 Paging Registers two stereo outputs, and one mono output channel. The Adjustable VREF amplifier STAC9752/9753 include digital output capability for support Digital-ready status of modern PC systems with an output that supports the SPDIF format. The STAC9752/9753 are standard General purpose I/Os 2-channel stereo CODECs. With TSIs headphone Crystal Elimination Circuit capability, headphones can be driven without an external Headphone drive capability (50 mW) amplifier. The STAC9752/9753 may be used as a secondary or tertiary CODECs, with 0dB, 10dB, 20dB, and 30dB microphone boost capability STAC9700/21/44/56/08/84/50/66 as the primary, in a +3.3 V (STAC9753) and +5 V (STAC9752) analog power multiple CODEC configuration conforming to the AC 97 supply options Rev. 2.3 specification. This configuration can provide the Pin compatible with the STAC9700, STAC9721, true six-channel, AC-3 playback required for DVD STAC9756 applications. The STAC9752/9753 communicate via the five AC-Link lines to any digital component of AC 97, 100% pin compatible with STAC9750 and STAC9766 providing flexibility in the audio system design. Packaged in TSI Surround (SS3D) Stereo Enhancement an AC 97 compliant 48-pin TQFP, the STAC9752/9753 can Energy saving dynamic power modes be placed on the motherboard, daughter boards, PCI, AMR, CNR, MDC or ACR cards. Multi-CODEC option (Intel AC 97 rev 2.3) Six analog line-level inputs Features 90dB SNR Line to Line High performance SD technology SNR > 89dB through Mixer and DAC AC97 Rev 2.3 compliant TSI CONFIDENTIAL 1 V 3.4 10/14 2014 TEMPO SEMICONDCUTOR, INC. STAC9752/9753STAC9752/9753 Two-Channel, 20-Bit, AC97 2.3 Codecs with Headphone Drive, SPDIF Output Microphone & Jack Sensing TABLE OF CONTENTS 1. TABLE OF CONTENTS ............................................................................................................ 2 1.1. List of Figures ....................................................................................................................................5 1.2. List of Tables .....................................................................................................................................6 2. PRODUCT BRIEF ..................................................................................................................... 7 2.1. Features .............................................................................................................................................7 2.2. Description .........................................................................................................................................7 2.3. STAC9752/53 Block Diagram ...........................................................................................................9 2.4. Key Specifications .............................................................................................................................9 2.5. Related Materials .............................................................................................................................10 2.6. Additional Support ...........................................................................................................................10 3. CHARACTERISTICS AND SPECIFICATIONS ....................................................................... 11 3.1. Electrical Specifications ...................................................................................................................11 3.1.1. Absolute Maximum Ratings: ..............................................................................................11 3.1.2. Recommended Operating Conditions ..............................................................................11 3.1.3. Power Consumption .........................................................................................................12 3.1.4. AC-Link Static Digital Specifications .................................................................................13 3.1.5. STAC9752 5V Analog Performance Characteristics .........................................................13 3.1.6. STAC9753 3.3V Analog Performance Characteristics ......................................................15 3.2. AC Timing Characteristics ...............................................................................................................17 3.2.1. Cold Reset .........................................................................................................................17 3.2.2. Warm Reset .....................................................................................................................17 3.2.3. Clocks ..............................................................................................................................18 3.2.4. STAC9752/53 Crystal Elimination Circuit and Clock Frequencies .....................................18 3.2.5. Data Setup and Hold ........................................................................................................19 3.2.6. Signal Rise and Fall Times ...............................................................................................19 3.2.7. AC-Link Low Power Mode Timing .....................................................................................20 3.2.8. ATE Test Mode .................................................................................................................20 4. TYPICAL CONNECTION DIAGRAM ...................................................................................... 21 4.1. Slit Independent Power Supply Operation .......................................................................................22 5. CONTROLLER, CODEC, AND AC-LINK ................................................................................ 23 5.1. AC-link Physical interface ................................................................................................................23 5.2. Controller to Single Codec ...............................................................................................................23 5.3. Controller to Multiple Codecs ...........................................................................................................25 5.3.1. Primary Codec Addressing ................................................................................................25 5.3.2. Secondary Codec Addressing ...........................................................................................26 5.3.3. Codec ID Strapping ............................................................................................................26 5.4. Clocking for Multiple Codec Implementations ..................................................................................26 5.5. STAC9752/53 as a Primary Codec ..................................................................................................27 5.5.1. STAC9752/53 as a Secondary Codec ...............................................................................27 5.6. AC-link Power Management ............................................................................................................27 5.6.1. Powering down the AC-link ................................................................................................27 5.6.2. Waking up the AC-link .......................................................................................................28 5.6.2.1. Controller Initiates Wake-up .............................................................................28 5.6.2.2. Codec Initiates Wake-up ..................................................................................28 5.6.3. Codec Reset ......................................................................................................................28 5.6.4. Cold AC 97 Reset .............................................................................................................29 5.6.5. Warm AC 97 Reset ...........................................................................................................29 5.6.6. Register AC 97 Reset .......................................................................................................29 6. AC-LINK DIGITAL INTERFACE ............................................................................................. 30 6.1. Overview ..........................................................................................................................................30 6.2. AC-link Serial Interface Protocol ......................................................................................................31 6.2.1. AC-link Variable Sample Rate Operation ...........................................................................31 6.2.2. Variable Sample Rate Signaling Protocol ..........................................................................32 6.2.2.1. SLOTREQ Behavior and Power Management .................................................33 6.2.3. Primary and Secondary Codec Register Addressing .........................................................33 6.3. AC-link Output Frame (SDATA OUT) ...........................................................................................34 6.3.1. Slot 0: TAG / Codec ID .....................................................................................................35 TSI CONFIDENTIAL 2 V 3.4 10/14 2014 TEMPO SEMICONDCUTOR, INC. STAC9752/9753