DATASHEET PORTABLE CONSUMER CODEC TSCS42XX LOW-POWER, HIGH-FIDELITY INTEGRATED CODEC DESCRIPTION FEATURES The TSCS42XX is a low-power, high-fidelity integrated CODEC High fidelity CODEC with 32 bit stereo playback stereo record functionality. In addition 2 DAC 102dB SNR to a high-fidelity low-power CODEC, the device integrates the true 2 ADC 90dB SNR cap-less headphone amplifier. 32 bit stereo DAC and 32-bit stereo ADC Sample rates of 8k to 96 kHz The digital audio data format (I2S) works in master or slave mode and supports all I2S formats as well as direct Bluetooth PCM Audio Output Processing DSP Engine mode. 3D stereo enhancement 12 band parametric equalizers Beyond high-fidelity for portable systems, the device offers an Dynamic Range controller enriched audio presence through built-in audio output - Multi-band compressor processing DSP engine (AOP). The AOP supports 12 Bands of - Limiter EQ, Psychoacoustic Bass and Treble enhancement, 3D stereo - Expander enhancement and Dynamic Range controller to support Psychoacoustic Bass and Treble enhancement Multi-band Compressor/Limiter capability. processing 3rd Party algorithms APPLICATIONS DDX Digital Speaker Driver Bluetooth Speakers 3W/channel 4 (1.5W/8) Portable Navigation Devices TSI DDX class D technology achieves low EMI and high efficiency Portable Gaming Devices >90% efficiency Personal Media Players Spread spectrum support for reduced EMI Constant output power mode Multimedia handsets Anti-Pop circuitry E-books Filterless architecture reduces BOM cost Chromebook /Tablets On-chip true cap-less headphone driver 35 mW output power (16 ) Charge-pump allows true ground centered outputs SNR (A-Weighted, no active signal) -122dB SNR (A-Weighted, -60db active signal) -102dB Headphone detection logic Microphone/line-in interface XTAL / CLK IN PLL GPIO I2C Internal XTAL OUT Audio Clocks Analog microphone or line-in inputs MCLK / MCLK2 / ADCBLCK / DACBCLK Automatic level control LIN1 I2S / PCM OUT LIN2 1 stereo DMIC ADC MUX LIN3 / DMIC SPK Out L BTL Class D D2S INPUT DSP PWM Low power with built in power management SPK Out R PROCESSOR RIN1 BTL 1.7 V CODEC supports 1Vrms RIN2 ADC MUX RIN3 / DMIC MUX Very low standby and no-signal power consumption D2S 1.8V digital / 1.7V analog supply for low power VREF MICBIAS1 CAP-LESS HP L DAC / LINEOUT L 2 I2S / PCM 2-wire (I C compatible) control interface DSP 2 LIN1 CAP-LESS HP R I S data interface DAC / LINEOUT R MUX LIN2 Supports Bluetooth mode + D2S D2S Left-Justified, Right-Justified and PCM Audio Interfaces LIN1 MUX CHARGE RIN2 HP DETECT package option PUMP 7x7 QFN w1 1 V 1.1 2/17 2017 TEMPO SEMICONDCUTOR, INC. TSCS42XXTSCS42XX Portable Consumer CODECs TABLE OF CONTENTS 1. OVERVIEW ................................................................................................................................ 8 1.1. Block Diagram ...................................................................................................................................8 1.2. Audio Outputs ....................................................................................................................................8 1.3. Audio Inputs .......................................................................................................................................9 2. POWER MANAGEMENT ........................................................................................................ 10 2.1. Control Registers .............................................................................................................................10 2.1.1. Power Management Register 1 .........................................................................................10 2.1.2. Power Management 2 Register ........................................................................................11 2.2. Stopping the Master Clock ...............................................................................................................11 3. OUTPUT AUDIO PROCESSING ............................................................................................. 12 3.1. DC Removal ....................................................................................................................................12 3.2. Volume Control ................................................................................................................................13 3.2.1. Volume Control Registers ..................................................................................................14 3.3. Parametric Equalizer .......................................................................................................................15 3.3.1. Prescaler & Equalizer Filter ...............................................................................................15 3.3.2. EQ Filter Enable Register .................................................................................................16 3.3.3. DACCRAM Write/Read Registers ......................................................................................16 3.3.3.1. DAC Coefficient Write Data Low Register .......................................................16 3.3.3.2. DAC Coefficient Write Data Mid Registe ..........................................................16 3.3.3.3. DAC Coefficient WRITE Data High RegisterI ...................................................17 3.3.3.4. DAC Coefficient Read Data Low Register ........................................................17 3.3.3.5. DAC Coefficient Read Data Mid Registe ..........................................................17 3.3.3.6. DAC Coefficient Read Data High RegisteI .......................................................17 3.3.4. DACCRAM Address Register ............................................................................................18 3.3.5. DACCRAM STATUS Register ...........................................................................................18 3.3.6. Equalizer, Bass, Treble Coefficient & Equalizer Prescaler RAM .......................................18 3.4. Gain and Dynamic Range Control ...................................................................................................22 3.5. Multi-band Compressor ....................................................................................................................23 3.5.1. Overview ............................................................................................................................23 3.5.2. Multi band Compressor Registers ......................................................................................25 3.6. Limiter/Compressor Registers .........................................................................................................31 3.6.1. Limiter ................................................................................................................................31 3.6.2. Configuration ......................................................................................................................33 3.6.3. Controlling parameters .......................................................................................................33 3.6.4. Limiter/Compressor/Expander Registers ...........................................................................34 3.6.4.1. General compressor/limiter/expander control Register ....................................34 3.6.4.2. Compressor/Limiter/Expander make-up gain Register ....................................34 3.6.4.3. Compressor Threshold Register .......................................................................34 3.6.4.4. Compressor ration register ...............................................................................35 3.6.4.5. Compressor Attack Time Constant Register (Low) ..........................................35 3.6.4.6. Compressor Attack Time Constant Register (High) ..........................................35 3.6.4.7. Compressor Release Time Constant Register (Low) .......................................35 3.6.4.8. Compressor Release Time Constant Register (High) ......................................36 3.6.4.9. Limiter Threshold Register ...............................................................................36 3.6.4.10. Limiter Target Register ...................................................................................36 3.6.4.11. Limiter Attack Time Constant Register (Low) .................................................36 3.6.4.12. Limiter Attack Time Constant Register (High) ................................................37 3.6.4.13. Limiter Release Time Constant Register (Low) ..............................................37 3.6.4.14. Limiter Release Time Constant Register (High) .............................................37 3.6.4.15. Expander Threshold Register .........................................................................37 3.6.4.16. Expander Ratio Register ................................................................................38 3.6.4.17. Expander Attack Time Constant Register (Low) ............................................38 3.6.4.18. Expander Attack Time Constant Register (High) ............................................38 3.6.5. Expander Release Time Constant Register (Low) .............................................................38 3.6.6. Expander Release Time Constant Register (High) ............................................................39 3.7. Output Effects ..................................................................................................................................39 3.7.1. FX Control Register ...........................................................................................................39 2 V 1.1 2/17 2017 TEMPO SEMICONDCUTOR, INC. TSCS42XX