DATASHEET VALUE-LINE TWO-CHANNEL AC97 CODECS STAC9750/9751 OVERVIEW RELATED MATERIALS Value-Line Stereo AC 97 CODECs with headphone drive Data Sheet and SPDIF outputs. Reference Designs for MB, CNR, ACR and PCI applications FEATURES Audio Precision Performance Plots Full Duplex Stereo 18-bit ADCs and 20-bit DACs DESCRIPTION AC97 Rev 2.2 Compliant High Performance Technology TSI s STAC9750/9751 are general purpose, full duplex, audio CODECs conforming to the analog component spec- SPDIF Output ification of AC 97 (Audio CODEC 97 Component Specifica- Crystal Elimination Circuit tion Rev. 2.2). They have 18-bit ADCs and 20-bit DACs. Headphone amplifier The STAC9750/9751 incorporate TSI s proprietary tech- nology to achieve a DAC SNR in excess of 89dB. Independent Sample Rates for ADCs & DACs (hardware SRCs) The DACs, ADCs and mixer are integrated with analog I/Os, which include four analog line-level stereo inputs, two 20dB or 30dB Microphone Boost Capability analog line-level mono inputs, two stereo outputs, and one 90dB SNR LINE-LINE mono output channel. 5-Wire AC-Link Protocol Compliance The STAC9750/9751 include digital input/output capability Digital-Ready Architecture for support of modern PC systems and also an output that supports the SPDIF format. General Purpose I/O The STAC9750/9751 is a standard 2-channel stereo +3.3 V (STAC9751) and +5 V (STAC9750) Analog CODEC. With TSIs headphone drive capability, head- Power Supply Options phones can be driven with no external amplifier. Pin Compatible With STAC9700/21/56/66 The STAC9750/9751 may be used as a secondary TSI Surround (SS3D) Stereo Enhancement CODEC, with the STAC9700/21/44/56/08/84/66 as the pri- Energy Saving Dynamic Power Modes mary, in a multiple CODEC configuration conforming to the AC 97 Rev. 2.2 specification. This configuration can provide KEY SPECIFICATIONS the true six-channel, AC-3 playback required for DVD appli- cations. Analog LINE OUT SNR: 90dB Digital DAC SNR: 89dB The STAC9750/9751 communicates via the five-wire AC-Link to any digital component of AC 97, providing flexi- Digital ADC SNR: 85dB bility in the audio system design. Full-scale Total Harmonic Distortion: 0.005% The STAC9750/9751 supports General Purpose Input/Out- Crosstalk between Input Channels: -70dB put (GPIO), as well as SPDIF output. These digital I/O Spurious Tone Rejection: 100dB options provide for a number of advanced architectural implementations, with volume controls and digital mixing capabilities built directly into the CODEC. Packaged in an AC 97 compliant 48-pin TQFP, the TSI CONFIDENTIAL 1 V 5.9 10/14 2014 TEMPO SEMICONDCUTOR, INC. STAC9750/9751STAC9750/9751 Value-Line Two-Channel AC97 Codecs TABLE OF CONTENTS 1. PRODUCT BRIEF ..................................................................................................................... 5 1.1. Features .............................................................................................................................................5 1.2. Description .........................................................................................................................................5 1.3. STAC9750/9751 Block Diagram ........................................................................................................6 1.4. Key Specifications .............................................................................................................................6 1.5. Related Materials ...............................................................................................................................7 1.6. Additional Support .............................................................................................................................7 2. CHARACTERISTICS/SPECIFICATIONS ................................................................................. 8 2.1. Electrical Specifications .....................................................................................................................8 2.2. AC Timing Characteristics ...............................................................................................................15 3. TYPICAL CONNECTION DIAGRAM ...................................................................................... 19 4. AC-LINK .................................................................................................................................. 20 4.1. Clocking ...........................................................................................................................................20 4.2. Reset ...............................................................................................................................................20 5. DIGITAL INTERFACE ............................................................................................................. 21 5.1. AC-Link Digital Serial Interface Protocol ..........................................................................................21 5.2. AC-Link Low Power Mode ...............................................................................................................28 5.3. Waking up the AC-Link ....................................................................................................................29 6. STAC9750/9751 MIXER .......................................................................................................... 30 6.1. Analog Mixer Input ...........................................................................................................................31 6.2. Analog Mixer Output ........................................................................................................................32 6.3. SPDIF Digital Mux ...........................................................................................................................32 6.4. PC Beep Implementation .................................................................................................................32 6.5. Programming Registers ...................................................................................................................33 7. LOW POWER MODES ............................................................................................................ 53 8. MULTIPLE CODEC SUPPORT ............................................................................................... 55 8.1. Primary/Secondary CODEC Selection .............................................................................................55 8.2. Secondary CODEC Register Access Definitions .............................................................................56 9. TESTABILITY .......................................................................................................................... 57 10. PIN DESCRIPTION ............................................................................................................... 58 10.1. Digital I/O .......................................................................................................................................59 10.2. Analog I/O ......................................................................................................................................60 10.3. Filter/References/GPIO .................................................................................................................61 10.4. Power and Ground Signals ............................................................................................................61 11. ORDERING INFORMATION ................................................................................................. 62 12. PACKAGE DRAWINGS ........................................................................................................ 63 12.1. 48-Pin LQFP ..................................................................................................................................63 13. SOLDER REFLOW PROFILE ............................................................................................... 64 13.1. Standard Reflow Profile Data ........................................................................................................64 13.2. Pb Free Process - Package Classification Reflow Temperatures .................................................64 14. APPENDIX A: SPLIT INDEPENDENT POWER SUPPLY OPERATION .............................. 65 15. APPENDIX B: PROGRAMMING REGISTERS ..................................................................... 67 16. REVISION HISTORY ............................................................................................................. 68 TSI CONFIDENTIAL 2 V 5.9 10/14 2014 TEMPO SEMICONDCUTOR, INC. STAC9750/9751