DATASHEET AC97 2.3 CODECS WITH STEREO MICROPHONE STAC9752A/9753A & UNIVERSAL JACK Reference Designs FEATURES High Performance SD Technology DESCRIPTION AC97 Rev 2.3 Complaint TSI s STAC9752A/9753A are general purpose 20-bit, full 20-bit Full Duplex Stereo ADC & DACs duplex, audio CODECs conforming to the analog compo- Independent Sample Rates for ADC & DACs nent specification of AC 97 (Audio CODEC 97 Component Specification Rev. 2.3). The STAC9752A/9753A incorpo- 5-Wire AC-Link Protocol Compliance rates TSI s proprietary SD technology. 20-Bit SPDIF Output The AC97 CODEC is designed to achieve a DAC SNR in Universal Jacks excess of 94dB. The DACs, ADCs, and mixer are inte- Full Stereo Microphone Pre-Amp grated with analog I/Os, which include four analog Internal Jack Sensing on Headphone & Line Out line-level stereo inputs, two analog line-level mono inputs, Internal Microphone Input Sensing two stereo outputs, and one mono output channel. Digital PC Beep Option The STAC9752A/9753A includes digital input/output capa- Extended AC97 2.3 Paging Registers bility for support of modern PC systems, with an output that supports the SPDIF format. The STAC9752A/9753A is a General Purpose I/Os and Crystal Elimination standard 2-channel stereo CODEC. With TSIs headphone Circuit drive capability, headphones can be driven with without an Headphone Drive Capability (50 mW per channel) external amplifier. Switchable Headphone Out (pins 39/41 or 35/36) The STAC9752A/9753A may be used as a secondary 0dB, 10dB, 20dB and 30dB Microphone Boost CODEC, with the STAC9700/21/56/08/84/50/52 as the pri- Capability mary, in a multiple CODEC configuration conforming to the +3.3 V (STAC9753A) and +5 V (STAC9752A) Analog AC 97 Rev. 2.3 specification. This configuration can provide Power Supply Options the true six-channel, AC-3 playback required for DVD appli- cations. Pin Compatible with STAC9750/52/66 The STAC9752A/9753A communicates via the five-wire KEY SPECIFICATIONS AC-Link to any digital component of AC 97, providing flexi- bility in the audio system design. Analog LINE OUT SNR: 94dB Digital DAC SNR: 92dB Packaged in an AC 97 compliant 48-pin TQFP, the STAC9752A/9753A can be placed on a motherboard, Digital ADC SNR: 85dB daughter boards, PCI, AMR, CNR, MDC or ACR cards. Full-scale Total Harmonic Distortion: 0.002% The STAC9752A/9753A provides variable sample rate Dig- Crosstalk Between Input Channels: -70dB ital-to-Analog (DA) and Analog-to-Digital (AD) conversion, Spurious Tone Rejection: 100dB mixing, and analog processing. Stereo Microphone Input Supported audio sample rates include 48 KHz, 44.1 KHz, 32 KHz, 22.05 KHz, 16 KHz, 11.025 KHz, and 8 KHz addi- RELATED MATERIALS tional rates are supported in the STAC9752A/9753A soft Data Sheet audio drivers. All ADCs and DACs operate at 20-bit resolu- TSI CONFIDENTIAL 1 V 1.6 10/14 2014 TEMPO SEMICONDCUTOR, INC. STAC9752A/9753ASTAC9752A/9753A AC97 2.3 CODECs with Stereo Microphone & Universal Jack TABLE OF CONTENTS PRODUCT BRIEF ......................................................................................................................... 6 Features ....................................................................................................................................................6 Description ................................................................................................................................................6 STAC9752A/9753A Block Diagram ..........................................................................................................8 Key Specifications ....................................................................................................................................8 Related Materials ......................................................................................................................................8 Additional Support ....................................................................................................................................9 CHARACTERISTICS AND SPECIFICATIONS ........................................................................... 10 Electrical Specifications ..........................................................................................................................10 Absolute Maximum Ratings .........................................................................................................10 Recommended Operation Conditions .........................................................................................10 Power Consumption ....................................................................................................................11 AC-Link Static Digital Specifications ............................................................................................11 STAC9752A Analog Performance Characteristics .......................................................................12 STAC9753A Analog Performance Characteristics .......................................................................13 AC Timing Characteristics ......................................................................................................................15 Cold Reset ...................................................................................................................................15 Warm Reset .................................................................................................................................15 Clocks ..........................................................................................................................................16 STAC9752A/9753A Crystal Elimination Circuit and Clock Frequencies ......................................16 Data Setup and Hold ...................................................................................................................17 Signal Rise and Fall Times ..........................................................................................................17 AC-Link Low Power Mode Timing ................................................................................................18 ATE Test Mode ............................................................................................................................18 TYPICAL CONNECTION AND POWER DIAGRAMS ................................................................. 20 STAC9752A/9753A Typical Connection Diagram for 48-pin LQFP ........................................................20 STAC9752A/9753A Typical Connection Diagram for 32-pad QFN ........................................................21 Split Independent Power Supply Operation ............................................................................................22 Split Independent Power Supply Operation for the 32-pad QFP Package .............................................23 CONTROLLER, CODEC, AND AC-LINK .................................................................................... 24 AC-Link Physical interface ......................................................................................................................24 Controller to Single CODEC ...................................................................................................................24 Controller to Multiple CODECs ...............................................................................................................25 Primary CODEC Addressing ........................................................................................................25 Secondary CODEC Addressing ...................................................................................................26 CODEC ID Strapping .....................................................................................................................6 Clocking for Multiple CODEC Implementations ......................................................................................26 STAC9752A/9753A as a Primary CODEC .............................................................................................26 STAC9752A/9753A as a Secondary CODEC ..............................................................................27 AC-Link Power Management ..................................................................................................................27 Powering down the AC-Link .........................................................................................................27 Waking up the AC-Link ................................................................................................................27 Controller Initiates Wake-up ..........................................................................................28 CODEC Initiates Wake-up .............................................................................................28 CODEC Reset ..............................................................................................................................28 Cold AC97 Reset ..........................................................................................................28 Warm AC97 Reset ........................................................................................................28 Register AC97 Reset ....................................................................................................29 AC-LINK DIGITAL INTERFACE ................................................................................................. 30 Overview .................................................................................................................................................30 AC-Link Serial Interface Protocol ............................................................................................................31 AC-Link Variable Sample Rate Operation ...................................................................................31 Variable Sample Rate Signaling Protocol ....................................................................................31 SLOTREQ Behavior and Power Management ..............................................................32 Primary and Secondary CODEC Register Addressing ................................................................33 AC-Link Output Frame (SDATA OUT) ...................................................................................................33 Slot 0: TAG / CODEC ID ..............................................................................................................35 TSI CONFIDENTIAL 2 V 1.6 10/14 2014 TEMPO SEMICONDCUTOR, INC. STAC9752A/9753A