78Q2123/78Q2133 MicroPHY 10/100BASE-TX Transeiver DATA SHEET JANUARY 2006 DESCRIPTION FEATURES TM The 78Q2123 and 78Q2133, MicroPHY , are the Smallest 10/100 PHY available smallest 10BASE-T/100BASE-TX Fast Ethernet 10BASE-T/100BASE-TX IEEE-802.3 compliant transceivers in the market. They include integrated TX and RX functions requiring a dual 1:1 MII, ENDECs, scrambler/descrambler, dual-speed isolation transformer interface to the line clock recovery, and full-featured auto-negotiation Integrated MII, 10BASE-T/100BASE-TX ENDEC, functions. The transmitter includes an on-chip pulse- 100BASE-TX scrambler/descrambler, and full- shaper and a low-power line driver. The receiver has featured auto-negotiation function an adaptive equalizer and a baseline restoration circuit required for accurate clock and data recovery. Full duplex operation capable The transceiver interfaces to Category-5 unshielded Automatic MDI/MDI-X cross over correction twisted pair (Cat-5 UTP) cabling for 100BASE-TX Register-programmable transmit amplitude applications, and Category-3 unshielded twisted pair (Cat-3 UTP) for 10BASE-T applications. The MDI is Automatic polarity correction during auto- connected to the line media via dual 1:1 isolation negotiation and 10BASE-T signal reception transformers. No external filter is required. Interface Power-saving and power-down modes to the MAC is accomplished through an IEEE-802.3 including transmitter disable compliant Media Independent Interface (MII). The 2 Programmable LED indicators (Link and 78Q2123/78Q2133 are intended to serve the Activity by default) embedded Ethernet market, tailored specifically to the needs of game consoles, broadband modems, User programmable Interrupt pin printers, set top boxes and audio/visual equipment. It Package: 32-QFN (5x5 mm) is designed for low-power consumption and operates Low Power (~290mW) from a single 3.3V supply. The 78Q2123 is rated for Single 3.3 V 0.3V Supply commercial temperature range and the 78Q2133 is rated for industrial temperature range. 78Q2123 rated for 0C to 70C operation 78Q2133 rated for -40C to 85C operation 4B/5B Encoder, 100M MRZ/NRZI Pulse Shaper Scrambler, MLT3 Encoder and Filter RXC Parallel/Serial Tx/Rx TXC TX CLK GEN Auto RXD MDI-X MII TXD 10M Parallel/Serial, Mux Rx/Tx Manchester Encoder SMI Auto Negotiation Carrier Sense, Collision Detect 10M 100M Manchester Decoder, Parallel/Serial CLK Adaptive EQ, Recovery MII Baseline Wander Correct, Registers Serial/Parallel MLT3 Decode, NRZI/NRZ Descrambler, LEDs Clock Reference 5B/4B Decoder Link Act 25MHz CLKIN Page: 1 of 39 2006 Teridian Semiconductor Corporation Rev 1.1 78Q2123/78Q2133 MicroPHY 10/100BASE-TX Transceiver Clock Selection FUNCTIONAL DESCRIPTION The 78Q2123/78Q2133 have an on-chip crystal GENERAL oscillator which can also be driven by an external oscillator. In this mode of operation, a 25MHz crystal Power Management should be connected between the XTLP and XTLN pins. Alternatively, an external 25MHz clock input The 78Q2123 and 78Q2133 have three power can be connected to the XTLP pin. In this mode of saving modes: operation, a crystal is not required and the XTLN pin Chip Power-Down must be tied to ground. Receive Power Management Transmit Clock Generation Transmit High Impedance Mode The transmitter uses an on-chip frequency Chip power-down is activated by setting the PWRDN synthesizer to generate the transmit clock. In bit in MII register MR0.11. When the chip is in 100BASE-TX operation, the synthesizer multiplies the power-down mode, all on-chip circuitry is shut off, reference clock by 5 to obtain the internal 125MHz and the device consumes minimum power. While in serial transmit clock. In 10BASE-T mode, it the power-down state, the 78Q2123/78Q2133 still generates an internal 20MHz transmit clock by respond to management transactions. multiplying the reference 25MHz clock by 4/5. The synthesizer references either the local 25 MHz crystal Receive power management (RXCC mode) is oscillator, or the externally applied clock, depending activated by setting the RXCC bit in MII register on the selected mode of operation. MR16.0. In this mode of operation, the adaptive equalizer, the clock recovery phase lock loop (PLL), Receive Signal Qualification and all other receive circuitry will be powered down when no valid MLT-3 signal is present at the UTP The integrated signal qualifier has separate squelch receive line interface. As soon as a valid signal is and unsquelch thresholds. It also includes a built-in detected, all circuits will automatically be powered timer to ensure fast and accurate signal detection and up to resume normal operation. During this mode of line noise rejection. Upon detection of two or more operation, RX CLK will be inactive when there is no valid 10BASE-T or 100BASE-TX pulses on the line data being received. Note that the RXCC mode is receive port, signal detect is indicated. The signal not supported during 10BASE-T operation. detect threshold is then lowered by about 40%. All adaptive circuits are released from their initial states Transmit high impedance mode is activated by and allowed to lock onto the incoming data. In setting the TXHIM bit in MII register MR16.12. In this 100BASE-TX operation, signal detect is de-asserted mode of operation, the transmit UTP drivers are in a when no signal is presented for a period of about high impedance state and TX CLK is tri-stated. A 1.2us. In 10BASE-T operation, signal detect is de- weak internal pull-up is enabled on TX CLK. The asserted whenever no Manchester data is received. In receive circuitry remains fully operational. The either case, the signal detect threshold will return to the default state of MR16.12 is a logic low for disabling squelched level whenever the signal detect indication the transmit high impedance mode. Only a reset is de-asserted. Signal detect is also used to control the condition will automatically clear MR16.12. The operation of the clock/data recovery circuit to assure transmitter is fully functional when MR16.12 is fast acquisition. cleared. This feature is useful when configuring a system for Wake-On LAN (when the Receive Clock Recovery 78Q2123/78Q2133 are coupled with a Wake-On LAN capable MAC). In 100BASE-TX mode, the 125MHz receive clock is extracted using a digital DLL-based loop. When no Analog Biasing and Supply Regulation receive signal is present, the CDR is directed to lock onto the 125MHz transmit serial clock. When signal The 78Q2123/78Q2133 require no external detect is asserted, the CDR will use the received MLT- component to generate on-chip bias voltages and 3 signal as the clock reference. The recovered clock is currents. High accuracy is maintained through a used to re-time the data signal and for conversion of closed-loop trimmed biasing network. the data to NRZ format. On-chip digital logic runs off an internal voltage regulator. Hence only a single 3.3V ( 0.3V) supply is required to power-up the device. The on-chip regulator is not affected by the power-down mode. Page: 2 of 39 2006 Teridian Semiconductor Corporation Rev 1.1