DF2B6USL ESD Protection Diodes Silicon Epitaxial Planar DF2B6USLDF2B6USLDF2B6USLDF2B6USL 1. 1. GeneralGeneral 1. 1. GeneralGeneral The DF2B6USL is a bidirectional TVS diode with low capacitance designed to protect IC devices from ESD and other transients voltage. By using original process, low dynamic resistance is incarnated, the clamp voltage can be suppressed to a low level. And ultra-compact package is ideal for high-density mounting. 2. 2. 2. 2. ApplicationsApplicationsApplicationsApplications Mobile Equipment Smartphones Tablets Notebook PCs USB 2.0 Note: This product is designed for protection against electrostatic discharge (ESD) and is not intended for any other purpose, including, but not limited to, voltage regulation. 3. 3. FeaturesFeatures 3. 3. FeaturesFeatures (1) Suitable for use with a 5 V signal line. (V 5.5 V) RWM (2) Protects devices with its high ESD performance. (V = 10 kV (Contact / Air) IEC61000-4-2) ESD (3) Low dynamic resistance protects semiconductor devices from static electricity and noise. (R = 0.25 (typ.)) DYN (4) Snapback characteristics realizing low clamping voltage protects semiconductor devices. (V = 7.7 V I = 1.5 A (typ.)) C PP (5) Compact package is suitable for use in high density board layouts such as in mobile devices. (0.62 mm 0.32 mm size (Nickname: SL2)) 4. 4. 4. 4. PackagingPackagingPackagingPackaging SL2 Start of commercial production 2016-09 2016-2018 2018-01-18 1 Toshiba Electronic Devices & Storage Corporation Rev.2.0DF2B6USL 5. 5. 5. 5. Example of Circuit DiagramExample of Circuit DiagramExample of Circuit DiagramExample of Circuit Diagram 6. 6. 6. 6. Quick Reference DataQuick Reference DataQuick Reference DataQuick Reference Data Characteristics Symbol Note Test Condition Min Typ. Max Unit Working peak reverse voltage V (Note 1) 5.5 V RWM Total capacitance C V = 0 V, f = 1 MHz 1.5 3.0 pF t R Dynamic resistance R (Note 2) 0.25 DYN Electrostatic discharge voltage V (Note 3) 10 kV ESD (IEC61000-4-2) (Contact) Note 1: Recommended operating condition. Note 2: TLP parameters: Z0 = 50 , tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns, extraction of dynamic resistance using least squares fit of TLP characteristics between I = 8 A and I = 16 A. PP1 PP2 Note 3: Criterion: No damage to devices. 6.1. 6.1. 6.1. 6.1. ESD Clamp Waveform (Note)ESD Clamp Waveform (Note)ESD Clamp Waveform (Note)ESD Clamp Waveform (Note) Fig. Fig. 6.1.16.1.1 +8 kV+8 kV Fig. Fig. 6.1.26.1.2 -8 kV-8 kV Fig. Fig. 6.1.16.1.1 +8 kV+8 kV Fig. Fig. 6.1.26.1.2 -8 kV-8 kV Fig. Fig. Fig. Fig. 6.1.36.1.36.1.36.1.3 IEC61000-4-2 (Contact)IEC61000-4-2 (Contact)IEC61000-4-2 (Contact)IEC61000-4-2 (Contact) Note: The above characteristics curves are presented for reference only and not guaranteed by production test, unless otherwise noted. 2016-2018 2018-01-18 2 Toshiba Electronic Devices & Storage Corporation Rev.2.0