TC58NVG2S3ETAI0 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 2 4 GBIT (512M 8 BIT) CMOS NAND E PROM DESCRIPTION The TC58NVG2S3E is a single 3.3V 4 Gbit (4,429,185,024 bits) NAND Electrically Erasable and Programmable 2 Read-Only Memory (NAND E PROM) organized as (2048 + 64) bytes 64 pages 4096blocks. The device has two 2112-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 2112-byte increments. The Erase operation is implemented in a single block unit (128 Kbytes + 4 Kbytes: 2112 bytes 64 pages). The TC58NVG2S3E is a serial-type memory device which utilizes the I/O pins for both address and data input/output as well as for command inputs. The Erase and Program operations are automatically executed making the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and other systems which require high-density non-volatile memory data storage. FEATURES Organization x8 Memory cell array 2112 256K 8 Register 2112 8 Page size 2112 bytes Block size (128K + 4K) bytes Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy, Multi Page Program, Multi Block Erase, Multi Page Copy, Multi Page Read Mode control Serial input/output Command control Number of valid blocks Min 4016 blocks Max 4096 blocks Power supply V = 2.7V to 3.6V CC Access time Cell array to register 30 s max Serial Read Cycle 25 ns min (CL=100pF) Program/Erase time Auto Page Program 300 s/page typ. Auto Block Erase 2.5 ms/block typ. Operating current Read (25 ns cycle) 30 mA max. Program (avg.) 30 mA max Erase (avg.) 30 mA max Standby 50 A max Package TSOP I 48-P-1220-0.50 (Weight: 0.53 g typ.) 1 2012-09-01 TC58NVG2S3ETAI0 PIN ASSIGNMENT (TOP VIEW) TC58NVG2S3ETAI0 8 8 NC 1 48 NC NC 2 47 NC NC 3 46 NC NC 4 45 NC NC 5 44 I/O8 NC 6 43 I/O7 RY /BY7 42 I/O6 RE 8 41 I/O5 CE 9 40 NC NC 10 39 NC NC 11 38 NC V 12 37 V CC CC V V 13 36 SS SS NC NC 14 35 NC 15 34 NC CLE 16 33 NC ALE I/O4 17 32 WE I/O3 18 31 WP 19 30 I/O2 NC I/O1 20 29 NC NC 21 28 NC 22 27 NC NC NC 23 26 NC 24 25 NC PINNAMES I/O1 to I/O8 I/O port CE Chip enable WE Write enable RE Read enable CLE Command latch enable ALE Address latch enable WP Write protect RY/BY Ready/Busy V Power supply CC V Ground SS 2 2012-09-01