TC74ACT161,163P/F/FN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74ACT161P,TC74ACT161F,TC74ACT161FN TC74ACT163P,TC74ACT163F,TC74ACT163FN Synchronous Presettable 4-Bit Binary Counter TC74ACT161P/F/FN Asynchronous Clear Note: xxxFN (JEDEC SOP) is not available in Japan. TC74ACT163P/F/FN Synchronous Clear TC74ACT161P, TC74ACT163P The TC74ACT161 and T163 are advanced high speed CMOS SYNCHRONOUS PRESETTABLE 4 BIT BINARY COUNTERs fabricated with silicon gate and double-layer metal wiring 2 C MOS technology. They achieve the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. These devices may be used as a level converter for interfacing TC74ACT161F, TC74ACT163F TTL or NMOS to High Speed CMOS. The inputs are compatible with TTL, NMOS and CMOS output voltage levels. The CK input is active on the rising edge. Both LOAD and CLR inputs are active on low logic level. Presetting of these ICs is synchronous to the rising edge of CK. The clear function of the TC74ACT163 is synchronous to CK, while the TC74ACT161 are cleared asynchronously. Two enable inputs (ENP and ENT) and CARRY OUTPUT are provided to enable easy cascading of counters, which facilitates easy implementation of n-bit counters without using external TC74ACT161FN, TC74ACT163FN gates. All inputs are equipped with protection circuits against static discharge or transient excess voltage. Features High speed: f = 110 MHz (typ.) at V = 5 V max CC Low power dissipation: I = 8 A (max) at Ta = 25C CC Compatible with TTL outputs: V = 0.8 V (max) IL Weight V = 2.0 V (min) IH DIP16-P-300-2.54A : 1.00 g (typ.) Symmetrical output impedance: I = I = 24 mA (min) OH OL SOP16-P-300-1.27A : 0.18 g (typ.) SOL16-P-150-1.27 : 0.13 g (typ.) Capability of driving 50 transmission lines. Balanced propagation delays: t t pLH pHL Pin and function compatible with 74F161/163 1 2007-10-01 TC74ACT161,163P/F/FN Pin Assignment IEC Logic Symbol TC74ACT161 TC74ACT163 Truth Table Inputs Outputs Function CLR CLR CK CK LOAD ENP ENT QA QB QC QD (161) (163) (161) (163) L L X X X X L L L L Reset to 0 H H L X X A B C D Preset Data H H H X L No Change No Count H H H L X No Change No Count H H H H H Count Up Count H X X X X No Change No Count X: Dont care A, B, C, D: Logic level of data inputs Carry: Carry = ENT QAQBQCQD 2 2007-10-01