TC75S51FUTE85LF Toshiba

TC75S51F/FU TOSHIBA CMOS Linear Integrated Circuit Silicon Monolithic TC75S51F, TC75S51FU Single Operational Amplifier TC75S51F The TC75S51F/TC75S51FU is a CMOS single-operation amplifier which incorporates a phase compensation circuit. It is designed with a low-voltage and low-current power supply this differentiates this device from general- purpose bipolar op-amps. Features Low-voltage operation : V = 0.75 to 3.5 V or 1.5 to 7 V DD (SMV) Low-current power supply : I (V = 3 V) = 60 A (typ.) TC75S51FU DD DD Built-in phase-compensated op-amp, obviating the need for any external device Ultra-compact package Absolute Maximum Ratings (Ta = 25C) (USV) Characteristics Symbol Rating Unit Weight Supply voltage V , V 7 V DD SS SSOP5-P-0.95 : 0.014 g (typ.) Differential input voltage DV 7 V IN SSOP5-P-0.65A : 0.006 g (typ.) Input voltage V V to V V IN DD SS Power dissipation P 200 mW D Operating temperature T 40 to 85 C opr Storage temperature T 55 to 125 C stg Note: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (Handling Precautions/Derating Concept and Methods) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Start of commercial production 1993-07 2019 2019-09-11 1 Toshiba Electronic Devices & Storage Corporation TC75S51F/FU Marking (top view) Pin Connection (top view) V OUT 5 4 DD 5 4 S C 1 2 3 IN (+) V IN () SS 1 2 3 Electrical Characteristics DC Characteristics (V = 3.0 V, V = GND, Ta = 25C) DD SS Test Characteristics Symbol Test Condition Min Typ. Max Unit Circuit Input offset voltage V 1 R = 1 k, R = 100 k 2 10 mV IO S F Input offset current I 1 pA IO Input bias current I 1 pA I Common mode input voltage CMV 2 R = 1 k, R = 100 k 0 2.5 V IN S F Voltage gain (open loop) G 60 70 dB V 3 R 100 k 2.9 VOH L Maximum output voltage V V 4 R 100 k 0.1 OL L Common mode input signal CMRR 2 V = 0.0 to 2.5 V 55 65 dB IN rejection ratio Supply voltage rejection ratio SVRR 1 V = 1.5 to 7.0 V 60 70 dB DD Supply current I 5 60 200 A DD DC Characteristics (V = 1.5 V, V = GND, Ta = 25C) DD SS Test Characteristics Symbol Test Condition Min Typ. Max Unit Circuit Input offset voltage V 1 R = 10 k, R = 100 k 2 10 mV IO S F Input offset current I 1 pA IO Input bias current I 1 pA I Common mode input voltage CMV 2 R = 10 k, R = 100 k 0 1.0 V IN S F Voltage gain (open loop) G 60 70 dB V V 3 R 100 k 1.4 OH L Maximum output voltage V V 4 R 100 k 0.1 OL L Supply current I 5 50 150 A DD Note: For this device, please use a source current of no more than 70 A. 2019 2019-09-11 2 Toshiba Electronic Devices & Storage Corporation