TC7W14FKTE85LF Toshiba

TC7W14FU/FK TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC7W14FU, TC7W14FK Schmitt Inverter 2 The TC7W14 is high speed C MOS Schmitt Inverter fabricated TC7W14FU 2 with silicon gate C MOS technology. It achieves the high speed operation similar to equivalent 2 LSTTL while maintaining the C MOS low power dissipation. Pin configuration and function are the same as the TC7WU04 but the inputs have 25% VCC hysteresis and with its Schmitt trigger function, the TC7W14 can be used as a line receivers which will receive slow input signals. All inputs are equipped with protection circuits against static discharge or transient excess voltage. (SM8) TC7W14FK Features High speed: t = 11 ns (typ.) at V = 5 V pd CC Low power dissipation: I = 1A (max) at Ta = 25C CC High noise immunity: V = 1.1 V at V = 5V H CC Output drive capability: 10 LSTTL loads Symmetrical output impedance: I = I = 4mA (min) OH OL Balanced propagation delays: t t pLH pHL Wide operating voltage range: V (opr) = 2 to 6V CC (US8) Weight Marking SSOP8-P-0.65: 0.02 g (typ.) SSOP8-P-0.50A: 0.01 g (typ.) TC7W14FU Part No. 7 W 1 4 Lot No. TC7W14FK Part No. W 1 4 Start of commercial production 1992-02 1 2014-11-10 TC7W14FU/FK Absolute Maximum Ratings (Ta = 25C) Characteristics Symbol Rating Unit Supply voltage range V 0.5 to 7 V CC DC input voltage V 0.5 to V + 0.5 V IN CC DC output voltage V 0.5 to V + 0.5 V OUT CC Input diode current I 20 mA IK Output diode current I 20 mA OK DC output current I 25 mA OUT DC V /ground current I 25 mA CC CC 300 (SM8) Power dissipation P mW D 200 (US8) Storage temperature range T 65 to 150 C stg Lead temperature (10 s) T 260 C L Note: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (Handling Precautions/Derating Concept and Methods) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Pin Configuration (top view) V 1Y 2Y CC 3A 8 7 5 6 1A 3Y 2A GND 1 2 3 4 Logic Diagram Truth Table A Y 1A 1Y L H H L 2A 2Y 3A 3Y 2 2014-11-10