DDR2 Unbuffered DIMM DDR2 Unbuffered DIMM is high-speed, low power memory module that use DDR2 SDRAM in FBGA package and a 2048 bits serial EEPROM on a 240-pin printed circuit board. DDR2 Unbuffered DIMM is a Dual In-Line Memory Module and is intended for mounting into 240-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operation frequencies, programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. Features Pin Identification RoHS compliant products. Symbol Function JEDEC standard 1.8V 0.1V Power supply A0~A13, BA0~BA2 Address/Bank input VDDQ=1.8V 0.1V DQ0~DQ63 Bi-direction data bus. DQS0~DQS7 Data strobes Clock Freq: 200MHZ for 400Mb/s/Pin /DQS0~/DQS7 Differential Data strobes 266MHZ for 533Mb/s/Pin. CK0, /CK0,CK1, /CK1 Clock Input. (Differential pair) 333MHZ for 667Mb/s/Pin. CK2, /CK2 400MHZ for 800Mb/s/Pin. CKE0, CKE1 Clock Enable Input. ODT0, ODT1 On-die termination control line Programmable CAS Latency: 3,4,5,6 /S0, /S1 DIMM rank select lines. Programmable Additive Latency : :0, 1, 2, 3, 4, 5 /RAS Row address strobe Write Latency (WL) = Read Latency (RL)-1 /CAS Column address strobe Burst Length: 4,8(Interleave/nibble sequential) /WE Write Enable Programmable sequential / Interleave Burst Mode DM0~DM7 Data masks/high data strobes VDD +1.8 Voltage power supply Bi-directional Differential Data-Strobe (Single-ended +1.8 Voltage Power Supply for data-strobe is an optional feature) VDDQ DQS Off-Chip Driver (OCD) Impedance Adjustment V Power Supply for Reference REF MRS cycle with address key programs. V SPD SPD EEPROM power supply DD SA0~SA2 Address select for EEPROM On Die Termination SCL Clock for EEPROM Serial presence detect with EEPROM SDA Data for EEPROM VSS Ground NC No Connection Dimensions (Normal Profile, Unit: millimeter) Note: 1. Tolerances on all dimensions +/-0.15mm unless otherwise specified.