DDR3 Unbuffered DIMM DDR3 Unbuffered DIMM is high-speed, low power memory module that use DDR3 SDRAM in FBGA package and a 2048 bits serial EEPROM on a 240-pin printed circuit board. DDR3 Unbuffered DIMM is a Dual In-Line Memory Module and is intended for mounting into 240-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operation frequencies, programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. Features Pin Identification RoHS compliant products. Symbol Function JEDEC standard 1.5V 0.075V Power supply A0~A15, BA0~BA2 Address/Bank input VDDQ=1.5V 0.075V DQ0~DQ63 Bi-direction data bus. DQS0~DQS7 Data strobes Clock Freq: 533MHZ for 1066Mb/s/Pin /DQS0~/DQS7 Differential Data strobes 667MHZ for 1333Mb/s/Pin. CK0, /CK0,CK1, /CK1 Clock Input. (Differential pair) 800MHZ for 1600Mb/s/Pin. CKE0, CKE1 Clock Enable Input. Programmable CAS Latency: 6, 7, 8, 9 ,10 ,11 ODT0, ODT1 On-die termination control line Programmable Additive Latency (Posted /CAS): /S0, /S1 DIMM rank select lines. /RAS Row address strobe 0,CL-2 or CL-1 clock /CAS Column address strobe Programmable /CAS Write Latency (CWL) /WE Write Enable = 6 (DDR3-1066),7 (DDR3-1333) , 8(DDR3-1600) DM0~DM7 Data masks/high data strobes 8 bit pre-fetch VDD Core power supply Burst Length: 4, 8 VDDQ I/O driver power supply Internal calibration through ZQ pin V DQ I/O reference supply REF On Die Termination with ODT pin Command/address reference V CA REF supply Serial presence detect with EEPROM V SPD SPD EEPROM power supply DD Asynchronous reset SA0~SA2 Address select for EEPROM SCL Clock for EEPROM SDA Data for EEPROM VSS Ground /RESET Set DRAMs Known State VTT SDRAM I/O termination supply NC No Connection Dimensions (Unit: millimeter) Note: 1. Tolerances on all dimensions +/-0.15mm unless otherwise specified.