APD-240G064 Vishay Dale Plasma Panel Display Modules 240 x 64 Graphics Display with ASCII Input Controller, DC/DC Converter and Drive Circuitry FEATURES 240 x 64 pixel array for bright and vivid graphics Parallel interface or RS-232 serial interface Powerful software commands make display integration simple and efficient + 5 to + 24VDC display voltage The APD-240G064 is a dot matrix graphic display with an STANDARD ELECTRICAL SPECIFICATIONS array of 240 x 64 pixels available. The module is composed of a highly reliable DC plasma display, ASCII input graphics control- DESCRIPTION MIN. TYP. MAX. UNITS SYMBOL ler, DC converter and drive circuitry which are assembled to form a rugged, slim profile display sub-system. Panel Supply Voltage VDC 5 12.0 24 V Interface to the APD-240G064 is through a parallel or serial inter- face. The interface allows for efficient handshaking and flow of Panel Supply Current 1.25 2.50** A bi-directional data. Vishay Dale s patented open construction IDC* display technology assures a stable, flicker free screen. Note: *at 12V **at start-up ENVIRONMENTAL SPECIFICATIONS OPTICAL SPECIFICATIONS Operating Temperature: 0C to - 70C Pixel Size: .019 .483mm Storage Temperature: - 20C to - 85C Pixel Array: 240 x 64 Operating Humidity: 95% RH non-condensing Luminance: 50 foot lamberts typical Mechanical Shock: 30G Color: Neon orange. Vibration: 0.018 .457mm displacement amplitude from Refresh Cycle: 65Hz 10-50Hz, 2G acceleration from 50 to 2000Hz logarithmic Viewing Angle: 150 cone sweep rate Mean Time Between Failure: 50,000 hours Contrast Ratio: 30:1 ELECTROSTATIC CAUTION Vishay Dale display panels use electrostatic sensitive components. These assemblies should be unpacked and handled in an ESD controlled area only. When shipping use packing materials designed for protection of electrostatic sensitive components. Vishay Dale believes that the information described in this publication is accurate and reliable, and much care has been taken in its preparation. However, no responsibility, financial or otherwise, is accepted for any consequences arising out of the use of this information. This information is subject to change without notice. DIMENSIONS in inches Mounting Holes .172 Dia. 4 Places .200 10.230 .325 Max. 4.3303.780 1.814 1.267 .275 7.409 1.610 1.3 Max. See Character Detail A .0285 .019 Sq. Typ031 Detail A Matrix Document Number: 37046 www.vishay.com Revision 21-Dec-00 41APD-240G064 Vishay Dale POWER SUPPLY: (Recommended) POWER SUPPLY CONNECTION CONNECTOR PIN SIGNAL 2.5A Max.*, 1.25 A Typ. VDC + 12V 0.6V J1 1 + 12 V 2 GROUND *Note: The maximum VDC draw denotes a power up condition 3 GROUND when the DC converter starts. Typical duration is 15-30 mS. 4 Reserved *Unit may be powered from + 5V to + 24V. Contact factory for Mates to Tyco AMP *1-480424-0 housing (1 rqr.) current draw at voltages other than + 12V and pin connection J2. *350689-1 socket pins (4 rqr.) Power up RESET cycle on display module takes approxi- POWER UP CONDITION mately Immediately upon power up the following is set: 250 mS to complete. It is suggested the user wait for that The module is in the text mode. time period to elapse before entering data. The screen will have a message printed as follows: PARALLEL INTERFACE RAM OK ROM OK J2, PARALLEL DATA CONNECTOR. mm-dd-yy Mates with 3M Tyco AMP 746285-6, 26 pin, IDC connector. This message indicates the hardware test has passed Note: PAR should be jumper selected on jumper block W1 for successfully. Themm-dd-y indicates the date the firm- proper parallel interface operation. ware was released. PARALLEL INTERFACE FUNCTION PIN DESCRIPTION D0-D7 (Data Bus) 1, 3, 5, 7, 9, 11, 13, 15 Data written to and read from the display unit through an 8 bit (input/output) bi-directional data bus. WRITE (WR) 17 Write data on low to high transmit. (input) 21 READ (RD) Read data while low. (input) 6, 8, 12, 14, 16, 18, 20, 22 Not connected. N/C Reset display to power-up condition when low, operate while high. 23 RESET (input) US (Unit Select) 19 Read and Write commands only influence display while US is low. (input) BLANK (BL) 25 Blank display while BL is low but maintain cursor and data. (input) BRIGHT/DIM (input) Display at full brightness when high or half brightness when low. 4 (BUSY (BU) 24 When BUSY is high, no further data or commands should be given. (output) GROUND 2, 26 Common to both power supply input and host data interface . 10 Data is ready to be read when the DATA PRESENT signal is high. DATA PRESENT (DP) (output) Note: Input load is one 74 HCT type input with 4.7k to V . Outputs cc INPUT/OUTPUT TIMING DIAGRAM, J2 are 74 HC type. BU Once data write is complete, BUSY signal is output. BUSY DP WR RD US FUNCTION signal =1 during data disposition and while the L X H L Write character or control code. communication buffer is full. X H H L L Read data from display while low. DATA WRITE: When WR changes from0 to1 while X X X X H Input/Output inhibited. US =0 and RD =1 , data is latched. LOGIC LEVEL: L = 0.0 V minimum to 0.8 V maximum. H = 2.2 V minimum to 5.0 V maximum.. DATA READ: When RD =0 while US =0 . WR =1 , and X = Don t care. DP =1 , data may be read by the host. www.vishay.com Document Number: 37046 42 Revision 21-Dec-00