DG2018, DG2019 Vishay Siliconix Low Voltage, Dual DPDT and Quad SPDT Analog Switches DESCRIPTION FEATURES The DG2018 and DG2019 are low voltage, single supply Low voltage operation (1.8 V to 5.5 V) analog switches. The DG2018 is a dual double-pole/double- Low on resistance throw (DPDT) with two control inputs that each controls a - R : 6 at 2.7 V DS(on) pair of single-pole/double-throw (SPDT). The DG2019 uses Low voltage logic compatible one control pin to operate four independent SPDT switches. - DG2019: V = 1 V INH When operated on a + 3 V supply, the DG2018s control pins High bandwidth: 180 MHz are compatible with 1.8 V digital logic. The DG2019 has an QFN-16 package available feature of a V pin that allows a 1.0 V threshold for L the control pin when V is powered with 1.5 V. L BENEFITS Built on Vishay Siliconixs low voltage submicron CMOS Ideal for both analog and digital signal switching process, the DG2018 and DG2019 are ideal for high Reduced power consumption performance switching of analog signals providing low on- High accuracy resistance (6 at + 2.7 V), fast speed (T , T at 42 ns and on off Reduced PCB space 16 ns), and a bandwidth that exceeds 180 MHz. Fast switching The DG2018 and DG2019 were designed to offer solutions Low leakage that extend beyond audio/video functions, to providing the performance required for todays demanding mixed-signal APPLICATIONS switching in portable applications. Cellular phones An epitaxial layer prevents latch-up. Brake-before-make is Audio and video signal routing guaranteed for all SPDTs. All switches conduct equally well PCMCIA cards in both directions when on, and blocks up to the power supply level when off. Battery operated systems Portable instrumentation FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION DG2018DN TRUTH TABLE QFN-16 (3 X 3) IN1, IN2 COM1 NO1 V+ NC4 Logic NC1 and NC2 NO1 and NO2 16 15 14 13 0ON OFF 1OFF ON IN3, IN4 NC1 COM4 1 12 Logic NC3 and NC4 NO3 and NO4 IN1, IN2 NO4 0ON OFF 2 11 1OFF ON NO2 IN3, IN4 3 10 COM2 NC3 49 ORDERING INFORMATION Temp. Range Package Part Number 56 7 8 - 40 C to 85 C QFN-16 (3 x 3 mm) DG2018DN NC2 GND NO3 COM3 Top View Document Number: 72342 www.vishay.com S-82626-Rev. C, 03-Nov-08 1DG2018, DG2019 Vishay Siliconix FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION DG2019DN QFN-16 (3 X 3) TRUTH TABLE COM1 NO1 V+ NC4 Logic NC1, 2, 3 and 4 NO1, 2, 3 and 4 16 15 14 13 0ON OFF 1OFF ON NC1 COM4 1 12 IN NO4 2 11 ORDERING INFORMATION Temp. Range Package Part Number NO2 V 3 10 L - 40 C to 85 C QFN-16 (3 x 3 mm) DG2019DN COM2 NC3 49 56 7 8 NC2 GND NO3 COM3 Top View ABSOLUTE MAXIMUM RATINGS Parameter Limit Unit Reference V+ to GND - 0.3 to + 6 V IN, COM, NC, NO - 0.3 to (V+ + 0.3) Continuous Current (Any terminal) 50 mA Peak Current (Pulsed at 1 ms, 10 % Duty Cycle) 100 Storage Temperature (D Suffix) - 65 to 150 C b c 850 mW Power Dissipation (Packages) QFN-16 (3 x 3 mm) Notes: a. Signals on NC, NO, or COM or IN exceeding V+ will be clamped by internal diodes. Limit forward diode current to maximum current ratings. b. All leads welded or soldered to PC board. c. Derate 4.0 mW/C above 70 C. www.vishay.com Document Number: 72342 2 S-82626-Rev. C, 03-Nov-08