DG221B Vishay Siliconix Quad SPST CMOS Analog Switch with Latches DESCRIPTION FEATURES Accepts 150 ns write pulse width The DG221B is a monolithic quad single-pole, single-throw Pb-free 5 V on-chip regulator analog switch designed for precision switching applications Available in communication, instrumentation and process control Latches are transparent with WR low RoHS* systems. COMPLIANT Low on-resistance: 60 W Featuring independent onboard latches and a common WR BENEFITS pin, each DG221B can be memory mapped, and addressed Compatible with most P buses as a single data byte for simultaneous switching. Allows wide power supply tolerance without affecting TTL The DG221B combines low power and low on-resistance compatibility (60 typical) while handling continuous currents up to 20 mA. Reduced power consumption An epitaxial layer prevents latchup. Allows flexibility of design The device features true bidirectional performance in the on APPLICATIONS condition. P based systems Automatic test equipment Communication systems Data acquisition systems Medical instrumentation Factory automation FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION Four latchable SPST switches per package Dual-In-Line and SOIC TRUTH TABLE IN IN IN 1 2 WR Switch 1 16 X 0 0 ON D D 1 2 2 15 10 OFF S S 1 2 3 14 Control data latched-in, switches on X or off as selected by last IN V- V+ X 4 13 X 1 Maintains previous state GND WR 5 12 Logic0 0.8 V S S Logic1 2.4 V 4 6 11 3 D D 4 3 7 10 IN IN 4 3 8 9 Top View * Pb containing terminations are not RoHS compliant, exemptions may apply. Document Number: 71616 www.vishay.com S-80263-Rev. B, 11-Feb-08 1 Input LatchDG221B Vishay Siliconix ORDERING INFORMATION Temp. Range Package Standard Part Number Lead (Pb)-free Part Number 16-Pin Plastic DIP DG221BDJ DG221BDJ-E3 - 40 C to 85 C DG221BDY DG221BDY-E3 16-Pin Narrow SOIC DG221BDY-T1 DG221BDY-T1-E3 ABSOLUTE MAXIMUM RATINGS Parameter Limit Unit Voltages Referenced V+ to V- 34 GND 25 V (V-) - 2 to (V+) + 2 a Digital Inputs , V , V S D or 20 mA, whichever occurs first Continuous Current (Any Terminal) 30 Continuous Current, S or D 20 mA Peak Current, S or D (Pulsed at 1 ms, 10 % duty cycle max.) 70 Storage Temperature (DJ and DY Suffix) - 65 to 125 C c 470 16-Pin Plastic DIP b mW Power Dissipation (Package) d 600 16-Pin SOIC Notes: a. Signals on S , D , or IN exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings. X X X b. All leads welded or soldered to PC board. c. Derate 6.5 mW/C above 25 C. d. Derate 7.7 mW/C above 75 C. SCHEMATIC DIAGRAM Typical Channel V+ 5 V S Reg GND V- IN - X Level + Latch Shift/ Drive V- V+ V+ WR - + D V- Figure 1. www.vishay.com Document Number: 71616 2 S-80263-Rev. B, 11-Feb-08