DG401, DG403, DG405 Vishay Siliconix Low-Power, High-Speed CMOS Analog Switches DESCRIPTION FEATURES 44 V supply max. rating The DG401, DG403, DG405 monolithic analog switches were designed to provide precision, high performance 15 V analog signal range switching of analog signals. Combining low power (0.35 W, On-resistance - R (on): 30 DS typ.) with high speed (t : 75 ns, typ.), the DG401 series is ON Low leakage - I : 40 pA D(on) ideally suited for portable and battery powered industrial and Fast switching - t : 75 ns ON military applications. Ultra low power requirements - P : 0.35 W D TTL, CMOS compatible Built on the Vishay Siliconix proprietary high-voltage Single supply capability silicon-gate process to achieve high voltage rating and superior switch on/off performance, break-before-make is Compliant to RoHS directive 2002/95/EC guaranteed for the SPDT configurations. An epitaxial layer prevents latchup. BENEFITS Wide dynamic range Each switch conducts equally well in both directions when Break-before-make switching action on, and blocks up to 30 V peak-to-peak when off. On- Simple interfacing resistance is very flat over the full 15 V analog range, rivaling JFET performance without the inherent dynamic APPLICATIONS range limitations. Audio and video switching Sample-and-hold circuits The three devices in this series are differentiated by the type Battery operation of switch action as shown in the functional block diagrams. Test equipment Communications systems PBX, PABX FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION DG401 DG401 LCC Dual-In-Line and SOIC NC D NC S IN 1 1 1 D S 1 1 Key 1 16 312 1 209 NC IN 1 2 15 4 18 NC V- NC V- Two SPST Switches per Package 3 14 5 17 NC GND NC GND TRUTH TABLE 4 13 6 16 Logic Switch NC NC NC V L 5 12 0 OFF 7 15 NC V NC V+ L 6 11 1ON 8 14 NC IN NC V+ 2 7 10 Logic0 0.8 V Logic1 2.4 V D S 2 2 8 9 910 11 12 13 NC D NC S IN 2 2 2 Top View Top View * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 70049 www.vishay.com S09-2561-Rev. I, 30-Nov-09 1DG401, DG403, DG405 Vishay Siliconix FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION DG403 DG403 LCC Dual-In-Line and SOIC NC D NC S IN 1 1 1 Key D S 1 1 312 1 209 1 16 NC IN 1 Two SPDT Switches per Package 2 15 4 18 D V- 3 D V- 3 3 14 TRUTH TABLE 5 17 S GND 3 S GND 3 Logic SW , SW SW , SW 4 13 1 2 3 4 6 16 NC NC S V 0 OFF ON 4 L 5 12 7 15 S V 4 L 1ON OFF D V+ 4 6 11 8 14 D V+ Logic0 0.8 V 4 NC IN 2 7 10 Logic1 2.4 V 910 11 12 13 D S 2 2 8 9 NC D NC S IN 2 2 2 Top View Top View DG405 DG405 LCC Dual-In-Line and SOIC NC D NC S IN 1 1 1 D S 1 1 1 16 Key 312 1 209 NC IN 1 2 15 Two DPST Switches per Package 4 18 D V- D V- 3 3 3 14 TRUTH TABLE 5 17 S GND S GND 3 3 4 13 Logic Switch 6 16 S V NC NC 4 L 5 12 0 OFF 7 D V+ 15 1ON 4 S V 4 L 6 11 8 14 Logic0 0.8 V NC IN 2 D V+ 4 7 10 Logic1 2.4 V D S 2 2 8 9 910 11 12 13 NC D NC S IN 2 2 2 Top View Top View www.vishay.com Document Number: 70049 2 S09-2561-Rev. I, 30-Nov-09