3.3 mm SiZ256DT www.vishay.com Vishay Siliconix Dual N-Channel 70 V (D-S) MOSFETs FEATURES PowerPAIR 3 x 3S G 2 TrenchFET Gen IV power MOSFETs S 2 S 2 8 S 7 2 6 100 % R and UIS tested g 5 Integrated MOSFET half bridge power stage D 1 Optimized Q /Q ratio improves switching gs gs characteristics 1 2 3 G 1 D Material categorization: for definitions of compliance 1 4 1 D 1 D 1 please see www.vishay.com/doc 99912 Top View Bottom View D 1 APPLICATIONS PRODUCT SUMMARY CHANNEL-1 CHANNEL-2 POL G1 V (V) 70 70 DS Synchronous buck converter N-Channel 1 R max. ( ) at V = 4.5 V 0.0176 0.0176 DS(on) GS S /D 1 2 Telecom DC/DC MOSFET R max. ( ) at V = 3.3 V 0.0200 0.0200 DS(on) GS Resonant converters Q typ. (nC) 8.2 8.2 g G 2 Motor drive control a I (A) 31.8 31.8 D N-Channel 2 MOSFET S Configuration Dual 2 ORDERING INFORMATION Package PowerPAIR 3 x 3S Lead (Pb)-free and halogen-free SiZ256DT-T1-GE3 ABSOLUTE MAXIMUM RATINGS (T = 25 C, unless otherwise noted) A PARAMETER SYMBOL CHANNEL-1 CHANNEL-2 UNIT Drain-source voltage V 70 70 DS V Gate-source voltage V 12 12 GS a a T = 25 C 31.8 31.8 C T = 70 C 25.4 25.4 C Continuous drain current (T = 150 C) I J D b, c b, c T = 25 C 11.5 11.5 A b, c b, c T = 70 C 9.2 9.2 A A Pulsed drain current (100 s pulse width) I 60 60 DM = 25 C 27 27 T C Continuous source drain diode current I S b, c b, c T = 25 C 3.6 3.6 A Single pulse avalanche current I 12 12 AS L = 0.1 mH Single pulse avalanche energy E 7.2 7.2 mJ AS T = 25 C 33 33 C T = 70 C 21 21 C Maximum power dissipation P W D b, c b, c T = 25 C 4.3 4.3 A b, c b, c T = 70 C 2.8 2.8 A Operating junction and storage temperature range T , T -55 to +150 J stg C d Soldering recommendations (peak temperature) 260 THERMAL RESISTANCE RATINGS CHANNEL-1 CHANNEL-2 PARAMETER SYMBOL UNIT TYP. MAX. TYP. MAX. b, f Maximum junction-to-ambient t 10 s R 23 29 23 29 thJA C/W Maximum junction-to-case (drain) Steady state R 3 3.833.8 thJC Notes a. T = 25 C C b. Surface mounted on 1 x 1 FR4 board c. t = 10 s d. See solder profile (www.vishay.com/doc 73257). The PowerPAIR 3 x 3S is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components f. Maximum under steady state conditions is 64 C/W for channel-1 and 64 C/W for channel-2 S20-0816-Rev. A, 26-Oct-2020 Document Number: 79711 1 For technical questions, contact: pmostechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000 3.3 mm S /D 1 2 (Pin 9) SiZ256DT www.vishay.com Vishay Siliconix SPECIFICATIONS (T = 25 C, unless otherwise noted) J PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static V = 0 V, I = 250 A Ch-1 70 - - GS D Drain-source breakdown voltage V V DS V = 0 V, I = 250 A Ch-2 70 - - GS D I = 10 mA Ch-1 - 41 - D V Temperature coefficient V /T DS DS J I = 10 mA Ch-2 - 42 - D mV/C I = 250 A Ch-1 - -3.2 - D V Temperature coefficient V /T GS(th) GS(th) J I = 250 A Ch-2 - -3.2 - D V = V , I = 250 A Ch-1 0.5 - 1.5 DS GS D Gate threshold voltage V V GS(th) V = V , I = 250 A Ch-2 0.5 - 1.5 DS GS D V = 0 V, V = 70 V Ch-1 - - 100 DS GS Gate source leakage I nA GSS V = 0 V, V = 12 V Ch-2 - - 100 DS GS V = 70 V, V = 0 V Ch-1 - - 1 DS GS V = 70 V, V = 0 V Ch-2 - - 1 DS GS Zero gate voltage drain current I A DSS V = 70 V, V = 0 V, T = 55 C Ch-1 - - 5 DS GS J V = 70 V, V = 0 V, T = 55 C Ch-2 - - 5 DS GS J V 5 V, V = 10 V Ch-1 7 - - DS GS b On-state drain current I A D(on) V 5 V, V = 10 V Ch-2 7 - - DS GS V = 4.5 V, I = 7 A Ch-1 - 0.0137 0.0176 GS D V = 4.5 V, I = 7 A Ch-2 - 0.0143 0.0176 GS D b Drain-source on-state resistance R DS(on) V = 3.3 V, I = 5 A Ch-1 - 0.0151 0.0200 GS D V = 3.3 V, I = 5 A Ch-2 - 0.0159 0.0200 GS D V = 10 V, I = 7 A Ch-1 - 85 - DS D b Forward transconductance g S fs V = 10 V, I = 7 A Ch-2 - 25 - DS D a Dynamic Ch-1 - 1060 - Input capacitance C iss Ch-2 - 1060 - Ch-1 - 125 - Channel-1 Output capacitance C pF oss V = 35 V, V = 0 V, f = 1 MHz DS GS Ch-2 - 125 - Ch-1 - 10 - Channel-2 Reverse transfer capacitance C rss V = 35 V, V = 0 V, f = 1 MHz Ch-2 - 10 - DS GS Ch-1 - - 0.0177 C /C ratio rss iss Ch-2 - - 0.0177 V = 35 V, V = 10 V, I = 10 A Ch-1 - 18 27 DS GS D V = 35 V, V = 10 V, I = 10 A Ch-2 - 18 27 DS GS D Total gate charge Q g V = 35 V, V = 4.5 V, I = 10 A Ch-1 - 8.2 13 DS GS D V = 35 V, V = 4.5 V, I = 10 A Ch-2 - 8.2 13 DS GS D Ch-1 - 2.6 - Channel-1 Gate-source charge Q nC gs V = 35 V, V = 4.5 V, I = 10 A DS GS D Ch-2 - 2.7 - Ch-1 - 1.7 - Channel-2 Gate-drain charge Q gd V = 35 V, V = 4.5 V, I = 10 A Ch-2 - 1.7 - DS GS D Ch-1 - 11 - Output charge Q V = 35 V, V = 0 V oss DS GS Ch-2 - 11 - Ch-1 0.26 1.3 2.6 Gate resistance R f = 1 MHz g Ch-2 0.2 1 2 S20-0816-Rev. A, 26-Oct-2020 Document Number: 79711 2 For technical questions, contact: pmostechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000