3 m3 mmm SiZ340BDT www.vishay.com Vishay Siliconix Dual N-Channel 30 V (D-S) MOSFETs FEATURES PowerPAIR 3 x 3 G 2 S TrenchFET Gen IV power MOSFETs 2 8 S 2 7 100 % R and UIS tested S g 2 6 5 S /D PowerPAIR integrated half-bridge MOSFET 1 2 (Pin 9) power stage D 1 Optimized Q /Q ratio improves switching gd gs 1 characteristics 2 G 1 3 Material categorization: for definitions of compliance D 1 11 4 D please see www.vishay.com/doc 99912 1 D 1 Top View Bottom View D APPLICATIONS 1 PRODUCT SUMMARY CPU core power CHANNEL-1 CHANNEL-2 G 1 Computer / server peripherals V (V) 30 30 DS N-Channel 1 S /D 1 2 POL MOSFET R max. () at V = 10 V 0.00856 0.00431 DS(on) GS Synchronous buck converter R max. () at V = 4.5 V 0.01403 0.00670 DS(on) GS G 2 Telecom DC/DC Q typ. (nC) 3.7 8.4 g N-Channel 2 a I (A) 36 69.3 MOSFET D S 2 Configuration Dual ORDERING INFORMATION Package PowerPAIR 3 x 3 Lead (Pb)-free and halogen-free SiZ340BDT-T1-GE3 ABSOLUTE MAXIMUM RATINGS (T = 25 C, unless otherwise noted) A PARAMETER SYMBOL CHANNEL-1 CHANNEL-2 UNIT Drain-source voltage V 30 30 DS V Gate-source voltage V +20, -16 +20, -16 GS T = 25 C 36 69.3 C T = 70 C 28.8 55.4 C Continuous drain current (T = 150 C) I J D b, c b, c T = 25 C 16.9 25.3 A b, c b, c T = 70 C 13.5 20.2 A A Pulsed drain current (100 s pulse width) I 100 150 DM T = 25 C 13.9 25.8 C Continuous source drain diode current I S b, c b, c T = 25 C 3.1 3.5 A Single pulse avalanche current I 10 15 AS L = 100 mH Single pulse avalanche energy E 511 mJ AS T = 25 C 16.7 31 C T = 70 C 10.7 20 C Maximum power dissipation P W D b, c b, c T = 25 C 3.7 4.2 A b, c b, c T = 70 C 2.4 2.7 A Operating junction and storage temperature range T , T -55 to +150 J stg C d Soldering recommendations (peak temperature) 260 THERMAL RESISTANCE RATINGS CHANNEL-1 CHANNEL-2 PARAMETER SYMBOL UNIT TYP. MAX. TYP. MAX. b, f Maximum junction-to-ambient t 10 s R 27 34 24 30 thJA C/W Maximum junction-to-case (drain) Steady state R 67.5 3.24 thJC Notes a. T = 25 C C b. Surface mounted on 1 x 1 FR4 board c. t = 10 s d. See solder profile (www.vishay.com/doc 73257). The PowerPAIR is a leadless package. The end of the lead terminal is exposed coppe r (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components f. Maximum under steady state conditions is 69 C/W for channel-1 and 64 C/W for channel-2 S20-0644-Rev. A, 24-Aug-2020 Document Number: 78132 1 For technical questions, contact: pmostechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000 3 mm3 mm SiZ340BDT www.vishay.com Vishay Siliconix SPECIFICATIONS (T = 25 C, unless otherwise noted) J PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static V = 0 V, I = 250 A Ch-1 30 - - GS D Drain-source breakdown voltage V V DS V = 0 V, I = 250 A Ch-2 30 - - GS D I = 10 mA Ch-1 - 25.1 - D V Temperature coefficient V /T DS DS J I = 10 mA Ch-2 - 24.3 - D mV/C I = 250 A Ch-1 - 4.0 - D V Temperature coefficient V /T GS(th) GS(th) J I = 250 A Ch-2 - 4.6 - D V = V , I = 250 A Ch-1 1.1 - 2.4 DS GS D Gate threshold voltage V V GS(th) V = V , I = 250 A Ch-2 1.1 - 2.4 DS GS D V = 0 V, V = +20 V / -16 V Ch-1 - - 100 DS GS Gate source leakage I nA GSS V = 0 V, V = +20 V / -16 V Ch-2 - - 100 DS GS V = 30 V, V = 0 V Ch-1 - - 1 DS GS V = 30 V, V = 0 V Ch-2 - - 1 DS GS Zero gate voltage drain current I A DSS V = 30 V, V = 0 V, T = 55 C Ch-1 - - 10 DS GS J V = 30 V, V = 0 V, T = 55 C Ch-2 - - 10 DS GS J V 5 V, V = 10 V Ch-1 15 - - DS GS b On-state drain current I A D(on) V 5 V, V = 10 V Ch-2 15 - - DS GS V = 10 V, I = 10 A Ch-1 - 0.00713 0.00856 GS D V = 10 V, I = 20 A Ch-2 - 0.00359 0.00431 GS D b Drain-source on-state resistance R DS(on) V = 4.5 V, I = 7 A Ch-1 - 0.01122 0.01403 GS D V = 4.5 V, I = 15 A Ch-2 - 0.00529 0.00670 GS D V = 10 V, I = 10 A Ch-1 - 30 - GS D b Forward transconductance g S fs V = 10 V, I = 10 A Ch-2 - 60 - GS D a Dynamic Ch-1 - 550 - Input capacitance C iss Ch-2 - 1065 - Ch-1 - 235 - Channel-1 Output capacitance C pF oss V = 15 V, V = 10 V, f = 1 MHz DS GS Ch-2 - 440 - Ch-1 - 30 - Channel-2 Reverse transfer capacitance C rss V = 15 V, V = 10 V, f = 1 MHz Ch-2 - 33 - DS GS Ch-1 - 0.052 0.103 C /C ratio rss iss Ch-2 - 0.031 0.062 V = 15 V, V = 10 V, I = 15 A Ch-1 - 8.4 12.6 DS GS D V = 15 V, V = 10 V, I = 20 A Ch-2 - 15.7 23.5 DS GS D Total gate charge Q g V = 15 V, V = 4.5 V, I = 15 A Ch-1 - 4.0 6.0 DS GS D V = 15 V, V = 4.5 V, I = 20 A Ch-2 - 7.3 11 DS GS D Ch-1 - 2.2 - Channel-1 Gate-source charge Q nC gs V = 15 V, V = 4.5 V, I = 15 A DS GS D Ch-2 - 3.9 - Ch-1 - 1.0 - Channel-2 Gate-drain charge Q gd V = 15 V, V = 4.5 V, I = 20 A Ch-2 - 1.7 - DS GS D Ch-1 - 0.9 - Output charge Q V = 15 V, V = 0 V oss DS GS Ch-2 - 1.4 - Ch-1 0.2 1 2 Gate resistance R f = 1 MHz g Ch-2 0.2 1 2 S20-0644-Rev. A, 24-Aug-2020 Document Number: 78132 2 For technical questions, contact: pmostechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000