6 mm6 mm SiZ998BDT www.vishay.com Vishay Siliconix Dual N-Channel 30 V (D-S) MOSFET With Schottky Diode FEATURES PowerPAIR 6 x 5 G 2 S TrenchFET Gen IV power MOSFET 2 8 S 2 7 SkyFET low side MOSFET with integrated S 2 6 5 Schottky S /D 1 2 (Pin 9) x Q FOM improves efficiency Very low R DS g D 1 1 100 % R and UIS tested g 2 G 1 3 Material categorization: for definitions of compliance D 1 4 11 D 1 please see www.vishay.com/doc 99912 D 1 Top View Bottom View D APPLICATIONS 1 PRODUCT SUMMARY CPU core power CHANNEL-1 CHANNEL-2 Computer / server peripherals G 1 V (V) 30 30 DS POL N-Channel 1 R max. () at V = 10 V 0.00439 0.0024 S /D DS(on) GS MOSFET Synchronous buck converter 1 2 R max. () at V = 4.5 V 0.00712 0.0038 DS(on) GS Telecom DC/DC Q typ. (nC) 5.7 14.6 g Schottky Diode a G I (A) 54.8 94.6 D 2 Dual plus integrated Schottky N-Channel 2 Configuration (SkyFET) MOSFET S 2 ORDERING INFORMATION Package PowerPAIR 6 x 5 Lead (Pb)-free and halogen-free SiZ998BDT-T1-GE3 ABSOLUTE MAXIMUM RATINGS (T = 25 C, unless otherwise noted) A PARAMETER SYMBOL CHANNEL-1CHANNEL-2UNIT Drain-source voltage V 30 30 DS V Gate-source voltage V +20, -16 +20, -16 GS T = 25 C 54.8 94.6 C T = 70 C 43.8 75.7 C Continuous drain current (T = 150 C) I J D b, c b, c T = 25 C 23.7 36.2 A b, c b, c T = 70 C 19 28.9 A A Pulsed drain current (t = 100 s) I 90 130 DM T = 25 C 16.7 27.4 C Continuous source-drain diode current I S b, c b, c T = 25 C 3.2 4 A Single pulse avalanche current I 15 20 AS L = 0.1 mH Single pulse avalanche energy E 11.2 20 mJ AS T = 25 C 20 32.9 C T = 70 C 12.9 21.1 C Maximum power dissipation P W D b, c b, c T = 25 C 3.8 4.8 A b, c b, c T = 70 C 2.4 3.1 A Operating junction and storage temperature range T , T -55 to +150 J stg C c, d Soldering recommendations (peak temperature) 260 THERMAL RESISTANCE RATINGS CHANNEL-1 CHANNEL-2 PARAMETER SYMBOL UNIT TYP. MAX. TYP. MAX. b, f Maximum junction-to-ambient t 10 s R 26 33 21 26 thJA C/W Maximum junction-to-case (drain) Steady state R 4.7 6.233.8 thJC Notes a. T = 25C C b. Surface mounted on 1 x 1 FR4 board c. t = 10 s d. See solder profile (www.vishay.com/doc 73257). The PowerPAIR is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is no t required to ensure adequate bottom side solder interconnection e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components f. Maximum under steady state conditions is 68 C/W for channel-1 and 57 C/W for channel-2 S20-0061-Rev. A, 10-Feb-2020 Document Number: 77875 1 For technical questions, contact: pmostechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000 5 mmSiZ998BDT www.vishay.com Vishay Siliconix SPECIFICATIONS (T = 25 C, unless otherwise noted) J PARAMETER SYMBOL TEST CONDITIONS MIN.TYP.MAX.UNIT Static Ch-1 30 - - Drain-source breakdown voltage V V = 0 V, I = 5 mA DS GS D Ch-2 30 - - Ch-1 36 - - Drain-source breakdown voltage V V = 0 V, t 1 s V c DSt GS transient (transient) Ch-2 36 - - Ch-1 1.2 - 2.2 Gate-source threshold voltage V V = V , I = 250 A GS(th) DS GS D Ch-2 1.1 - 2.2 Ch-1 - - 100 Gate-source leakage I V = 0 V, V = +20 V, -16 V nA GSS DS GS Ch-2 - - 100 Ch-1 - - 1 V = 30 V, V = 0 V DS GS Ch-2 - 40 200 Zero gate voltage drain current I A DSS Ch-1 - - 5 V = 30 V, V = 0 V, T = 55 C DS GS J Ch-2 - 200 2000 Ch-1 20 - - b On-state drain current I V 5 V, V = 10 V A D(on) DS GS Ch-2 20 - - V = 10 V, I = 15 A Ch-1 - 0.00338 0.00439 GS D V = 10 V, I = 19 A Ch-2 - 0.0018 0.0024 GS D b Drain-source on-state resistance R DS(on) V = 4.5 V, I = 12 A Ch-1 - 0.00547 0.00712 GS D V = 4.5 V, I = 15 A Ch-2 - 0.0026 0.0038 GS D V = 10 V, I = 15 A Ch-1 - 55 - DS D b Forward transconductance g S fs V = 10 V, I = 19 A Ch-2 230 - DS D a Dynamic Ch-1 - 790 - Input capacitance C iss Ch-2 - 2130 - Channel-1 Ch-1 - 390 - V = 15 V, V = 0 V, f = 1 MHz Output capacitance C DS GS pF oss Ch-2 - 1050 - Ch-1 - 38 - Reverse transfer capacitance C rss Channel-2 Ch-2 - 40 - V = 15 V, V = 0 V, f = 1 MHz DS GS Ch-1 - 0.046 0.092 C /C ratio rss iss Ch-2 0.019 0.038 V = 15 V, V = 10 V, I = 19 A Ch-1 - 12 18 DS GS D V = 15 V, V = 10 V, I = 19 A Ch-2 - 31.1 46.7 DS GS D Total gate charge Q g V = 15 V, V = 4.5 V, I = 19 A Ch-1 5.7 8.6 DS GS D V = 15 V, V = 4.5 V, I = 19 A Ch-2 - 14.6 21.9 DS GS D Ch-1 - 3 - Channel-1 Gate-source charge Q nC gs V = 15 V, V = 4.5 V, I = 19 A DS GS D Ch-2 - 7.1 - Ch-1 - 1.4 - Channel-2 Gate-drain charge Q gd V = 15 V, V = 4.5 V, I = 19 A Ch-2 - 3.4 - DS GS D Ch-1 - 10 - Output charge Q V = 15 V, V = 0 V oss DS GS Ch-2 - 30 - Ch-1 0.2 1.1 2.2 Gate resistance R f = 1 MHz g Ch-2 0.16 0.8 1.6 S20-0061-Rev. A, 10-Feb-2020 Document Number: 77875 2 For technical questions, contact: pmostechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000