5.13mm SQJ940EP www.vishay.com Vishay Siliconix Automotive Dual N-Channel 40 V (D-S) 175 C MOSFETs FEATURES PRODUCT SUMMARY TrenchFET Power MOSFET N-CHANNEL 1 N-CHANNEL 2 d AEC-Q101 Qualified V (V) 40 40 DS 100 % R and UIS Tested g R ( ) at V = 10 V 0.0160 0.0064 DS(on) GS Material categorization: R ( ) at V = 4.5 V 0.0188 0.0076 DS(on) GS For definitions of compliance please see I (A) 15 18 D www.vishay.com/doc 99912 Configuration Dual N PowerPAK SO-8L Asymmetric D D 1 2 D 2 G G 1 2 D 1 4 G 2 3 S 2 S S 2 1 2 G 1 1 S 1 N-Channel 1 MOSFET N-Channel 2 MOSFET Bottom View ORDERING INFORMATION Package PowerPAK SO-8L Dual Asymmetric Lead (Pb)-free and Halogen-free SQJ940EP-T1-GE3 ABSOLUTE MAXIMUM RATINGS (T = 25 C, unless otherwise noted) C PARAMETER SYMBOLN-CHANNEL 1 N-CHANNEL 2 UNIT Drain-Source Voltage V 40 40 DS V Gate-Source Voltage V 20 GS T = 25 C 15 18 C a Continuous Drain Current I D T = 125 C 15 10.5 C a Continuous Source Current (Diode Conduction) I 15 39 A S b Pulsed Drain Current I 60 72 DM Single Pulse Avalanche Current I 20.5 35.5 AS L = 0.1 mH Single Pulse Avalanche Energy E 21 63 mJ AS T = 25 C 48 43 C b Maximum Power Dissipation P W D T = 125 C 16 14 C Operating Junction and Storage Temperature Range T , T - 55 to + 175 J stg C e, f Soldering Recommendations (Peak Temperature) 260 THERMAL RESISTANCE RATINGS PARAMETER SYMBOL N-CHANNEL 1 N-CHANNEL 2 UNIT c Junction-to-Ambient PCB Mount R 70 70 thJA C/W Junction-to-Case (Drain) R 3.3 3.5 thJC Notes a. Package limited. b. Pulse test pulse width 300 s, duty cycle 2 %. c. When mounted on 1 square PCB (FR4 material). d. Parametric verification ongoing. e. See solder profile (www.vishay.com/doc 73257). The PowerPAK SO-8L is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection. f. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components. S13-0567-Rev. A, 18-Mar-13 Document Number: 62767 1 For technical questions, contact: automostechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000 6.15mm SQJ940EP www.vishay.com Vishay Siliconix SPECIFICATIONS (T = 25 C, unless otherwise noted) C PARAMETER SYMBOL TEST CONDITIONS MIN.TYP.MAX.UNIT Static V = 0 V, I = 250 A N-Ch 1 40 - - GS D Drain-Source Breakdown Voltage V DS V = 0 V, I = 250 A N-Ch 2 40 - - GS D V V = V , I = 250 A N-Ch 1 1.5 2 2.5 DS GS D Gate-Source Threshold Voltage V GS(th) V = V , I = 250 A N-Ch 2 1.5 2 2.5 DS GS D N-Ch 1 - - 100 Gate-Source Leakage I V = 0 V, V = 20 V nA GSS DS GS N-Ch 2 - - 100 V = 0 V V 40 V N-Ch 1 - - 1 GS DS V = 0 V V = - 40 V N-Ch 2 - - 1 GS DS V = 0 V V = 40 V, T = 125 C N-Ch 1 - - 50 GS DS J Zero Gate Voltage Drain Current I A DSS V = 0 V V = 40 V, T = 125 C N-Ch 2 - - 50 GS DS J V = 0 V V = 40 V, T = 175 C N-Ch 1 - - 150 GS DS J V = 0 V V = 40 V, T = 175 C N-Ch 2 - - 150 GS DS J V = 10 V V 5 V N-Ch 1 30 - - GS DS a On-State Drain Current I A D(on) V = 10 V V 5 V N-Ch 2 30 - - GS DS V = 10 V I = 15 A N-Ch 1 - 0.0133 0.0160 GS D V = 10 V I = 20 A N-Ch 2 - 0.0053 0.0064 GS D V = 10 V I = 15 A, T = 125 C N-Ch 1 - - 0.0270 GS D J V = 10 V I = 20 A, T = 125 C N-Ch 2 - - 0.0105 GS D J a Drain-Source On-State Resistance R DS(on) V = 10 V I = 15 A, T = 175 C N-Ch 1 - - 0.0334 GS D J V = 10 V I = 20 A, T = 175 C N-Ch 2 - - 0.0130 GS D J V = 4.5 V I = 13 A N-Ch 1 - 0.0157 0.0188 GS D V = 4.5 V I = 18 A N-Ch 2 - 0.0063 0.0076 GS D V = 15 V, I = 15 A N-Ch 1 - 64 - DS D b Forward Transconductance g S fs V = 15 V, I = 20 A N-Ch 2 - 102 - DS D b Dynamic V = 0 V V = 20 V, f = 1 MHz N-Ch 1 - 717 896 GS DS Input Capacitance C iss V = 0 V V = 20 V, f = 1 MHz N-Ch 2 - 1850 2313 GS DS V = 0 V V = 20 V, f = 1 MHz N-Ch 1 - 118 148 GS DS Output Capacitance C pF oss V = 0 V V = 20 V, f = 1 MHz N-Ch 2 - 272 340 GS DS V = 0 V V = 20 V, f = 1 MHz N-Ch 1 - 48 60 GS DS Reverse Transfer Capacitance C rss V = 0 V V = 20 V, f = 1 MHz N-Ch 2 - 98 123 GS DS V = 10 V V = 20 V, I = 6 A N-Ch 1 - 13.5 20 GS DS D c Q Total Gate Charge g V = 10 V V = 20 V, I = 16 A N-Ch 2 - 31.8 48 GS DS D V = 10 V V = 20 V, I = 6 A N-Ch 1 - 2.24 - GS DS D nC c Gate-Source Charge Q gs V = 10 V V = 20 V, I = 16 A N-Ch 2 - 5.5 - GS DS D V = 10 V V = 20 V, I = 6 A N-Ch 1 - 2.06 - GS DS D c Gate-Drain Charge Q gd V = 10 V V = 20 V, I = 16 A N-Ch 2 - 4.7 - GS DS D N-Ch 1 1.2 2.52 5 Gate Resistance R f = 1 MHz g N-Ch 2 3 7.93 13 Notes a. Pulse test pulse width 300 s, duty cycle 2 %. b. Guaranteed by design, not subject to production testing. c. Independent of operating temperature. S13-0567-Rev. A, 18-Mar-13 Document Number: 62767 2 For technical questions, contact: automostechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000