VS-ST300SPbF Series www.vishay.com Vishay Semiconductors Phase Control Thyristors (Stud Version), 300 A FEATURES Center amplifying gate International standard case TO-118 (TO-209AE) Hermetic metal case with ceramic insulator Threaded studs UNF 3/4 -16UNF-2A or TO-118 (TO- 209AE) ISO M24 x 1.5 Compression bonded encapsulation for heavy duty operations such as severe thermal cycling Designed and qualified for industrial level PRIMARY CHARACTERISTICS Material categorization: for definitions of compliance I 300 A T(AV) please see www.vishay.com/doc 99912 400 V, 800 V, 1200 V, 1600 V, V /V DRM RRM 1800 V, 2000 V TYPICAL APPLICATIONS V 1.28 V TM DC motor controls I 200 mA GT Controlled DC power supplies T -40 C to +125 C J AC controllers Package TO-118 (TO-209AE) Circuit configuration Single SCR MAJOR RATINGS AND CHARACTERISTICS PARAMETER TEST CONDITIONS VALUES UNITS 300 A I T(AV) T 75 C C I 470 T(RMS) 50 Hz 8000 A I TSM 60 Hz 8380 50 Hz 320 2 2 I t kA s 60 Hz 292 V /V 400 to 2000 V DRM RRM t Typical 100 s q T -40 to 125 C J ELECTRICAL SPECIFICATIONS VOLTAGE RATINGS V /V , MAXIMUM REPETITIVE V , MAXIMUM NON-REPETITIVE I /I MAXIMUM AT DRM RRM RSM DRM RRM VOLTAGE TYPE NUMBER PEAK AND OFF-STATE VOLTAGE PEAK VOLTAGE T = T MAXIMUM J J CODE V V mA 04 400 500 08 800 900 12 1200 1300 VS-ST300S 50 16 1600 1700 18 1800 1900 20 2000 2100 Revision: 27-Sep-17 Document Number: 94406 1 For technical questions within your region: DiodesAmericas vishay.com, DiodesAsia vishay.com, DiodesEurope vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000VS-ST300SPbF Series www.vishay.com Vishay Semiconductors ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL TEST CONDITIONS VALUESUNITS 180 conduction, half sine wave 300 A Maximum average on-state current I T(AV) at case temperature 75 C Maximum RMS on-state current I DC at 64 C case temperature 470 T(RMS) t = 10 ms 8000 No voltage reapplied t = 8.3 ms 8380 A Maximum peak, one-cycle I TSM non-repetitive surge current t = 10 ms 6730 100 % V RRM reapplied t = 8.3 ms 7040 Sinusoidal half wave, initial T = T maximum J J t = 10 ms 320 No voltage reapplied t = 8.3 ms 292 2 2 2 Maximum I t for fusing I t kA s t = 10 ms 226 100 % V RRM reapplied t = 8.3 ms 207 2 2 2 Maximum I t for fusing I t t = 0.1 ms to 10 ms, no voltage reapplied 3200 kA s Low level value of threshold voltage V (16.7 % x x I < I < x I ), T = T maximum 0.97 T(TO)1 T(AV) T(AV) J J V High level value of threshold voltage V (I > x I ), T = T maximum 0.98 T(TO)2 T(AV) J J Low level value of on-state slope resistance r (16.7 % x x I < I < x I ), T = T maximum 0.74 t1 T(AV) T(AV) J J m High level value of on-state slope resistance r (I > x I ), T = T maximum 0.73 t2 T(AV) J J Maximum on-state voltage V I = 940 A, T = T maximum, t = 10 ms sine pulse 1.66 V TM pk J J p Maximum holding current I 600 H T = 25 C, anode supply 12 V resistive load mA J Typical latching current I 1000 L SWITCHING PARAMETER SYMBOL TEST CONDITIONS VALUESUNITS Maximum non-repetitive rate of rise Gate drive 20 V, 20 , t 1 s r dI/dt 1000 A/s of turned-on current T = T maximum, anode voltage 80 % V J J DRM Gate current 1 A, dI /dt = 1 A/s g Typical delay time t 1.0 d V = 0.67 % V , T = 25 C d DRM J s I = 550 A, T = T maximum, dI/dt = 40 A/s, TM J J Typical turn-off time t 100 q V = 50 V, dV/dt = 20 V/s, gate 0 V 100 , t = 500 s R p BLOCKING PARAMETER SYMBOL TEST CONDITIONS VALUESUNITS Maximum critical rate of rise of dV/dt T = T maximum linear to 80 % rated V 500 V/s J J DRM off-state voltage Maximum peak reverse and I , RRM T = T maximum, rated V /V applied 30 mA J J DRM RRM off-state leakage current I DRM Revision: 27-Sep-17 Document Number: 94406 2 For technical questions within your region: DiodesAmericas vishay.com, DiodesAsia vishay.com, DiodesEurope vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000