KC705 Evaluation Board for the Kintex-7 FPGA User Guide UG810 (v1.9) February 4, 2019Revision History The following table shows the revision history for this document. Date Version Revision 02/04/2019 1.9 Updated the Electrostatic Discharge Caution section. In the DDR3 Memory Module, added information about configuration. Updated Appendix C, Xilinx Design Constraints and Appendix F, Regulatory and Compliance Information. 07/10/2018 1.8.1 Editorial updates only. No technical content updates. 03/20/2018 1.8 In Table 1-1, Quad SPI Flash Memory, and Ref 6 , added Micron MT25QL128ABA8ESF-0SIT as a possible part for U7. In Table 1-24, the I2C addresses were updated for the FMC HPC and FMC LPC device rows. 07/08/2016 1.7 Updated VRP/VRN resistor connection information in DDR3 Memory Module. Moved the Additional Resources and Legal Notices appendix to the end of the book. 08/26/2015 1.6.2 In Table 1-9, the I/O standard for SYSCLK N and SYSCLK P were updated to LVDS. In Table 1-27, under Directional Pushbutton Switches, the I/O standard for GPIO SW C was updated to LVCMOS25. Updated the USB UART section of Appendix C, Xilinx Design Constraints. 04/13/2015 1.6.1 In HPC Connector J22, the GTX clock count changed from 1 to 2. Updated links. 12/08/2014 1.6 Added a note about jumper header locations below Table 1-1. Changed Table 1-5 heading J1 DDR3 Memory to U58 BPI Flash Memory. Parts PC28F00AP30TF and N25Q128A13BSF40F changed from Numonyx to Micron. Described J11 and J12 connections in User SMA Clock Input. Made these updates in Programmable User Clock Source: XTP186 became XTP204, RDF0175 became RDF0194, XTP187 became XTP203, and RDF0176 became RDF0193. Corrected the device in the heading of Table 1-20 from CP2013 to CP2103. Updated I2C Bus Switch. Updated Table 1-24 I2C devices. In Table 1-28, J22 pin G7 connects to FPGA U1 pin C27. Replaced Table A-3, KC705 Default Jumper Settings and added Figure A-3 to show jumper locations. Replaced the constraints file in Appendix C, Xilinx Design Constraints. Added information about ordering the custom ATX cable to Appendix F, Regulatory and Compliance Information, Ref 21 . 07/11/2014 1.5 Corrected MGT Quad connection information in GTX Transceivers and a connection in Table 1-10. Added MGTREFCLK1 - PCIE CLK from P1 to Quad 115 in GTX Transceivers. Updated Table 1-4, Table 1-5, Table 1-6, Table 1-7, Table 1-9, Table 1-18, Table 1-21, Table 1-23, Table 1-27, Table 1-28, and Table 1-29. Added table footnotes regarding I/O standard and pins prior to board revision 1.1 to Table 1-14. Clarified default jumper positions in Table 1-15. Corrected the J2 C19 pin number in Table 1-29. In Figure 1-39, changed pin names VBATT to VCCBATT and POUC B to PUDC B. Removed three pins from See the Kintex-7 KC705 Evaluation Kit product page Documentation tab for the latest versions of the FPGA pins constraints files (XDC files). (PACKAGE PIN R8, R7, and W8). The Appendix C title changed to Master Constraints File Listing and the constraints file in Appendix C was replaced. The Declaration of Conformity link in Appendix F was updated. KC705 Evaluation Board 2 Send Feedback UG810 (v1.9) February 4, 2019 www.xilinx.com