KCU105 Board User Guide UG917 (v1.10) February 6, 2019Revision History The following table shows the revision history for this document. Date Version Revision 02/06/2019 1.10 Revised Electrostatic Discharge Caution. Added memory component information in DDR4 Component Memory. Replaced pin AM9 with D28 in Table 1-13. Revised appendix title and removed constraints file listing in Appendix D, Xilinx Design Constraints. Updated Markings in Appendix G, Regulatory and Compliance Information. 05/08/2018 1.9 Updated System Clock Source and Table 1-19. 07/26/2017 1.8 Updated Table 1-22 and Table 1-23. Added Documentation Navigator and Design Hubs. 01/12/2017 1.7 Revised Programmable User Clock Source, FMC HPC Connector J22, FMC LPC Connector J2, and Switches. Revised Figure A-1. 03/31/2016 1.6 Updated Table 1-11. 03/24/2016 1.5 Updated Figure 1-21. Changed the IOSTANDARD LVCMOS18 line in KCU105 Board Constraints File Listing on page 120. Added board thickness to Dimensions. Updated the Declaration of Conformity. 09/25/2015 1.4 Updated FMC HPC Connector J22. Revised Figure 1-23. Updated the binary format for I2C EEPROM in Table 1-19. Updated the clocks constraints file listing in Appendix D, Master Constraints File Listing. 06/27/2015 1.3 Updated connectivity information for Quad 226, Quad 227, and Quad 228 in GTH Transceivers. Updated Figure 1-21 and Figure 1-36. Updated HDMI Video Output, including updating Figure 1-22 and Table 1-18. 05/20/2015 1.2.1 Made typographical edits. 05/07/2015 1.2 Updated Table 1-17, Table 1-21, and Figure 1-22. 04/07/2015 1.1 Changed the Si5328C clock multiplier/jitter attenuator to Si5328B throughout, including updating the frequency range. Added impedance and insertion loss information to GTH SMA Clock Input, GTH TX and RX SMA Differential Pairs, PCI Express Endpoint Connectivity, SFP/SFP+ Module Connectors, FMC HPC Connector J22, and FMC LPC Connector J2. Updated Figure 1-2, Figure 1-8, Figure 1-9, Figure 1-22, Figure 1-23, Figure 1-29, Figure 1-34, Figure 1-36, Figure A-1, Figure C-1, and Figure C-2. Changed IIC to I2C throughout. Updated Table 1-4 and Table 1-25. Added Table 1-26, Maxim Power Tool GUI Regulator Settings. Updated information for J11, J47, and J49 in Table A-2. Updated callout number in KCU105 Board Zynq-7000 SoC XC7Z010 System Controller. Added instructions for accessing the system controller main menu in Appendix C, System Controller. Updated Clock Menu section. Updated the KCU105 Board Constraints File Listing in Appendix D. Updated the KCU105 evaluation kit master answer record number. 12/18/2014 1.0 Initial Xilinx release. KCU105 Board User Guide 2 Send Feedback UG917 (v1.10) February 6, 2019 www.xilinx.com