10 XA Spartan-6 Automotive FPGA Family Overview DS170 (v1.3) December 13, 2012 Product Specification General Description The Xilinx Automotive (XA) Spartan-6 family of FPGAs provides leading system integration capabilities with the lowest total cost for high- volume automotive applications. The ten-member family delivers expanded densities ranging from 3,840 to 101,261 logic cells and faster, more comprehensive connectivity. Built on a mature 45 nm low-power copper process technology that delivers the optimal balance of cost, power, and performance, the XA Spartan-6 family offers a new, more efficient, dual-register 6-input look-up table (LUT) logic and a rich selection of built-in system-level blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second generation DSP48A1 slices, SDRAM memory controllers, enhanced mixed-mode clock management blocks, SelectIO technology, power-optimized high-speed serial transceiver blocks, PCI Express compatible Endpoint blocks, advanced system-level power management modes, auto-detect configuration options, and enhanced IP security with AES and Device DNA protection. These features provide a low-cost programmable alternative to custom ASIC products with unprecedented ease of use. XA Spartan-6 FPGAs offer the best solution for flexible and scalable high-volume logic designs, high-bandwidth parallel DSP processing designs, and cost-sensitive applications where multiple interfacing standards are required. XA Spartan-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components that enable designers to focus on innovation as soon as their development cycle begins. Summary of XA Spartan-6 FPGA Features XA Spartan-6 Family: Integrated Memory Controller blocks XA Spartan-6 LX FPGA: Logic optimized DDR, DDR2, DDR3, and LPDDR support XA Spartan-6 LXT FPGA: High-speed serial connectivity Data rates up to 800 Mb/s Multi-port bus structure with independent FIFO to reduce Automotive Temperatures: design timing issues I-Grade: Tj = 40C to +100C Q-Grade: Tj = 40C to +125C Abundant logic resources with increased logic capacity Optional shift register or distributed RAM support Automotive Standards: Efficient 6-input LUTs improve performance and minimize Xilinx is ISO-TS16949 compliant power AEC-Q100 qualification LUT with dual flip-flops for pipeline centric applications Production Part Approval Process (PPAP) documentation Beyond AEC-Q100 qualification is available upon request Block RAM with a wide range of granularity Fast block RAM with byte write enable Designed for low cost 18 Kb blocks that can be optionally programmed as two Multiple efficient integrated blocks independent 9 Kb block RAMs Optimized selection of I/O standards Staggered pads Clock Management Tile (CMT) for enhanced performance High-volume plastic wire-bonded packages Low noise, flexible clocking Digital Clock Managers (DCMs) eliminate clock skew and Low static and dynamic power duty cycle distortion 45 nm process optimized for cost and low power Phase-Locked Loops (PLLs) for low-jitter clocking Hibernate power-down mode for zero power Frequency synthesis with simultaneous multiplication, Suspend mode maintains state and configuration with multi- division, and phase shifting pin wake-up, control enhancement Sixteen low-skew global clock networks High performance 1.2V core voltage (LX and LXT FPGAs, -2 and -3 speed grades) Simplified configuration, supports low-cost standards 2-pin auto-detect configuration Multi-voltage, multi-standard SelectIO interface banks Broad third-party SPI (up to x4) and NOR flash support Up to 1,080 Mb/s data transfer rate per differential I/O MultiBoot support for remote upgrade with multiple Selectable output drive, up to 24 mA per pin bitstreams, using watchdog protection 3.3V to 1.2V I/O standards and protocols Low-cost HSTL and SSTL memory interfaces Enhanced security for design protection Hot swap compliance Unique Device DNA identifier for design authentication Adjustable I/O slew rates to improve signal integrity AES bitstream encryption in the XA6SLX75, XA6SLX75T, High-speed GTP serial transceivers in the LXT FPGAs and XA6SLX100 devices Up to 3.2 Gb/s Integrated Endpoint block for PCI Express designs (LXT) High-speed interfaces including: Serial ATA and PCI Express Low-cost PCI technology support compatible with the 33 MHz, Efficient DSP48A1 slices 32- and 64-bit specification. High-performance arithmetic and signal processing Faster embedded processing with enhanced, low cost, Fast 18 x 18 multiplier and 48-bit accumulator MicroBlaze 32-bit soft processor Pipelining and cascading capability Industry-leading IP and reference designs Pre-adder to assist filter applications Strong automotive-specific third-party ecosystem with IP, development boards, and design services Copyright 20102012 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property of their respective owners. DS170 (v1.3) December 13, 2012 www.xilinx.com Product Specification 1XA Spartan-6 Automotive FPGA Family Overview XA Spartan-6 FPGA Feature Summary Table 1: XA Spartan-6 FPGA Feature Summary by Device Configurable Logic Blocks (CLBs) Block RAM Blocks Memory Endpoint Maximum Total Max Logic DSP48A1 Controller (5) Device Max CMTs Blocks for GTP I/O User (1) (3) Cells Slices Blocks (2) (4) Slices Flip-Flops Distributed 18 Kb Max (Kb) PCI Express Transceivers Banks I/O (Max) RAM (Kb) XA6SLX4 3,840 600 4,800 75 8 12 216 2 0 0 0 4 132 XA6SLX9 9,152 1,430 11,440 90 16 32 576 2 2 0 0 4 200 XA6SLX16 14,579 2,278 18,224 136 32 32 576 2 2 0 0 4 232 XA6SLX25 24,051 3,758 30,064 229 38 52 936 2 2 0 0 4 266 XA6SLX45 43,661 6,822 54,576 401 58 116 2,088 4 2 0 0 4 320 XA6SLX75 74,637 11,662 93,296 692 132 172 3,096 6 2 0 0 4 328 XA6SLX100 101,261 15,822 126,576 976 180 268 4,824 6 2 0 0 4 326 XA6SLX25T 24,051 3,758 30,064 229 38 52 936 2 2 1 2 4 250 XA6SLX45T 43,661 6,822 54,576 401 58 116 2,088 4 2 1 4 4 296 XA6SLX75T 74,637 11,662 93,296 692 132 172 3,096 6 2 1 4 4 268 Notes: 1. XA Spartan-6 FPGA logic cell ratings reflect the increased logic cell capability offered by the new 6-input LUT architecture. 2. Each XA Spartan-6 FPGA slice contains four LUTs and eight flip-flops. 3. Each DSP48A1 slice contains an 18 x 18 multiplier, an adder, and an accumulator. 4. Block RAMs are fundamentally 18 Kb in size. Each block can also be used as two independent 9 Kb blocks. 5. Each CMT contains two DCMs and one PLL. FPGA Device Package Combinations and Available I/Os XA Spartan-6 FPGA package combinations with the available I/Os and GTP transceivers per package are shown in Table 2. Due to the transceivers, the LX and LXT pinouts are not compatible. Table 2: XA Spartan-6 Device-Package Combinations and Maximum Available I/Os (1) (2) (3) (3) Package CSG225 FTG256 CSG324 CSG484 FGG484 Size (mm) 13x13 17x17 15x15 19x19 23 x 23 Pitch (mm) 0.8 1.0 0.8 0.8 1.0 Device User I/O User I/O GTPs User I/O GTPs User I/O GTPs User I/O XA6SLX4 132 XA6SLX9 160 186 NA 200 XA6SLX16 160 186 NA 232 XA6SLX25 186 NA 226 NA 266 XA6SLX45 NA 218 NA 320 NA 316 XA6SLX75 NA 328 NA 280 XA6SLX100 NA 326 XA6SLX25T 2 190 2 250 XA6SLX45T 4 190 4 296 XA6SLX75T 4 268 Notes: 1. XA Spartan-6 devices are available in Pb-free packages only. 2. Memory controller block support is x8 on the XA6SLX9 and XA6SLX16 devices in the CSG225 package. There is no memory controller in the XA6SLX4. 3. These packages support two of the four memory controllers in the XA6SLX75, XA6SLX75T, and XA6SLX100 devices. DS170 (v1.3) December 13, 2012 www.xilinx.com Product Specification 2