XA9572XL-15VQG44Q Xilinx

0 R XA9572XL Automotive CPLD 00 DS599 (v1.1) April 3, 2007 Product Specification Features Description The XA9572XL is a 3.3V CPLD targeted for high-perfor- AEC-Q100 device qualification and full PPAP support mance, low-voltage automotive applications. It is comprised available in both extended temperature Q-grade and of four 54V18 Function Blocks, providing 1,600 usable I-grade. gates with propagation delays of 15.5 ns. See Figure 2 for Guaranteed to meet full electrical specifications over overview. T = -40 C to +105 C with T Maximum = +125 C A J Power Estimation (Q-grade) 15.5 ns pin-to-pin logic delays Power dissipation in CPLDs can vary substantially depend- System frequency up to 64.5 MHz ing on the system frequency, design application and output 72 macrocells with 1,600 usable gates loading. Each macrocell in an XA9500XL automotive device Available in small footprint packages must be configured for low-power mode (default mode for XA9500XL devices). In addition, unused product-terms and - 44-pin VQFP (34 user I/O pins) macrocells are automatically deactivated by the software to - 64-pin VQFP (52 user I/O pins) further conserve power. - 100-pin TQFP (72 user I/O pins) - Pb-free package only For a general estimate of I , the following equation may be CC used: Optimized for high-performance 3.3V systems - Low power operation I (mA) = MC(0.052*PT + 0.272) + 0.04 * MC * MC * f CC TOG - 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V where: signals - 3.3V or 2.5V output capability MC = macrocells - Advanced 0.35 micron feature size CMOS PT = average number product terms per macrocell Fast FLASH technology Advanced system features f = maximum clock frequency - In-system programmable MC = average % of flip-flops toggling per clock TOG - Superior pin-locking and routability with (~12%) Fast CONNECT II switch matrix - Extra wide 54-input Function Blocks This calculation was derived from laboratory measurements - Up to 90 product-terms per macrocell with of an XA9500XL part filled with 16-bit counters and allowing individual product-term allocation a single output (the LSB) to be enabled. The actual I CC - Local clock inversion with three global and one value varies with the design application and should be veri- product-term clocks fied during normal system operation. Figure 1 shows the - Individual output enable per output pin above estimation in a graphical form. For a more detailed - Input hysteresis on all user and boundary-scan pin discussion of power consumption in this device, see Xilinx inputs application note XAPP114, Understanding XC9500XL - Bus-hold circuitry on all user pin inputs CPLD Power. - Full IEEE Standard 1149.1 boundary-scan (JTAG) 75 Fast concurrent programming Slew rate control on individual outputs 50 Enhanced data security features 64.5 MHz Excellent quality and reliability 25 - Endurance exceeding 10,000 program/erase cycles - 20 year data retention 0 100 50 - ESD protection exceeding 2,000V Clock Frequency (MHz) DS599 01 121106 WARNING: Programming temperature range of Figure 1: Typical I vs. Frequency for XA9572XL CC T = 0 C to +70 C A 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at R XA9572XL Automotive CPLD 3 JTAG In-System Programming Controller 1 JTAG Port Controller 54 Function 18 Block 1 I/O Macrocells I/O 1 to 18 I/O 54 I/O Function 18 Block 2 Macrocells 1 to 18 I/O Blocks I/O 54 Function I/O 18 Block 3 Macrocells I/O 1 to 18 I/O 3 I/O/GCK 54 Function 1 18 I/O/GSR Block 4 2 Macrocells I/O/GTS 1 to 18 DS057 02 082800 Figure 2: XA9572XL Architecture Function Block outputs (indicated by the bold line) drive the I/O Blocks directly. 2 www.xilinx.com DS599 (v1.1) April 3, 2007 Product Specification Fast CONNECT II Switch Matrix