R Spartan-II FPGA Family Data Sheet DS001 June 13, 2008 Product Specification This document includes all four modules of the Spartan -II FPGA data sheet. Module 1: Module 3: Introduction and Ordering Information DC and Switching Characteristics DS001-1 (v2.8) June 13, 2008 DS001-3 (v2.8) June 13, 2008 Introduction DC Specifications - Absolute Maximum Ratings Features - Recommended Operating Conditions General Overview - DC Characteristics Product Availability - Power-On Requirements User I/O Chart - DC Input and Output Levels Ordering Information Switching Characteristics - Pin-to-Pin Parameters Module 2: - IOB Switching Characteristics Functional Description - Clock Distribution Characteristics DS001-2 (v2.8) June 13, 2008 - DLL Timing Parameters - CLB Switching Characteristics Architectural Description - Block RAM Switching Characteristics - Spartan-II Array - TBUF Switching Characteristics - Input/Output Block - JTAG Switching Characteristics - Configurable Logic Block -Block RAM Module 4: - Clock Distribution: Delay-Locked Loop Pinout Tables - Boundary Scan Development System DS001-4 (v2.8) June 13, 2008 Configuration Pin Definitions - Configuration Timing Pinout Tables Design Considerations IMPORTANT NOTE: This Spartan-II FPGA data sheet is in four modules. Each module has its own Revision History at the end. Use the PDFBookmark for easy navigation in this volume. 2000-2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. DS001 June 13, 2008 www.xilinx.com Product Specification 16 Spartan-II FPGA Family: R Introduction and Ordering Information 0 DS001-1 (v2.8) June 13, 2008 Product Specification System level features Introduction - SelectRAM hierarchical memory: The Spartan -II Field-Programmable Gate Array family 16 bits/LUT distributed RAM gives users high performance, abundant logic resources, Configurable 4K bit block RAM and a rich feature set, all at an exceptionally low price. The Fast interfaces to external RAM six-member family offers densities ranging from 15,000 to - Fully PCI compliant 200,000 system gates, as shown in Table 1. System - Low-power segmented routing architecture performance is supported up to 200 MHz. Features include - Full readback ability for verification/observability block RAM (to 56K bits), distributed RAM (to 75,264 bits), - Dedicated carry logic for high-speed arithmetic 16 selectable I/O standards, and four DLLs. Fast, - Efficient multiplier support predictable interconnect means that successive design - Cascade chain for wide-input functions iterations continue to meet timing requirements. - Abundant registers/latches with enable, set, reset The Spartan-II family is a superior alternative to - Four dedicated DLLs for advanced clock control mask-programmed ASICs. The FPGA avoids the initial - Four primary low-skew global clock distribution cost, lengthy development cycles, and inherent risk of nets conventional ASICs. Also, FPGA programmability permits - IEEE 1149.1 compatible boundary scan logic design upgrades in the field with no hardware replacement Versatile I/O and packaging necessary (impossible with ASICs). - Pb-free package options - Low-cost packages available in all densities Features - Family footprint compatibility in common packages Second generation ASIC replacement technology - 16 high-performance interface standards - Densities as high as 5,292 logic cells with up to - Hot swap Compact PCI friendly 200,000 system gates - Zero hold time simplifies system timing - Streamlined features based on Virtex FPGA Core logic powered at 2.5V and I/Os powered at 1.5V, architecture 2.5V, or 3.3V - Unlimited reprogrammability Fully supported by powerful Xilinx ISE development - Very low cost system - Cost-effective 0.18 micron process - Fully automatic mapping, placement, and routing Table 1: Spartan-II FPGA Family Members CLB Maximum Total Total Logic System Gates Array Total Available Distributed RAM Block RAM (1) Device Cells (Logic and RAM) (R x C) CLBs User I/O Bits Bits XC2S15 432 15,000 8 x 12 96 86 6,144 16K XC2S30 972 30,000 12 x 18 216 92 13,824 24K XC2S50 1,728 50,000 16 x 24 384 176 24,576 32K XC2S100 2,700 100,000 20 x 30 600 176 38,400 40K XC2S150 3,888 150,000 24 x 36 864 260 55,296 48K XC2S200 5,292 200,000 28 x 42 1,176 284 75,264 56K Notes: 1. All user I/O counts do not include the four global clock/user input pins. See details in Table 2, page 4. 2000-2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. DS001-1 (v2.8) June 13, 2008 www.xilinx.com Module 1 of 4 Product Specification 2