Product Not Recommended For New Designs
1
R Virtex-II Pro and Virtex-II Pro X Platform FPGAs:
Complete Data Sheet
0
DS083 (v5.0) June 21, 2011 Product Specification
Module 1: Module 3:
Introduction and Overview DC and Switching Characteristics
10 pages 59 pages
Summary of Features Electrical Characteristics
General Description Performance Characteristics
Architecture Switching Characteristics
IP Core and Reference Support Pin-to-Pin Output Parameter Guidelines
Device/Package Combinations and Maximum I/O Pin-to-Pin Input Parameter Guidelines
Ordering Information DCM Timing Parameters
Source-Synchronous Switching Characteristics
Module 2:
Module 4:
Functional Description
Pinout Information
60 pages
302 pages
Functional Description: RocketIO X Multi-Gigabit
Transceiver
Pin Definitions
Functional Description: RocketIO Multi-Gigabit
Pinout Tables
Transceiver
- FG256/FGG256 Wire-Bond Fine-Pitch BGA Package
Functional Description: Processor Block
- FG456/FGG456 Wire-Bond Fine-Pitch BGA Package
- FG676/FGG676 Wire-Bond Fine-Pitch BGA Package
Functional Description: PowerPC 405 Core
- FF672 Flip-Chip Fine-Pitch BGA Package
Functional Description: FPGA
- FF896 Flip-Chip Fine-Pitch BGA Package
- Input/Output Blocks (IOBs)
- FF1148 Flip-Chip Fine-Pitch BGA Package
- Digitally Controlled Impedance (DCI)
- FF1152 Flip-Chip Fine-Pitch BGA Package
- On-Chip Differential Termination
- FF1517 Flip-Chip Fine-Pitch BGA Package
- Configurable Logic Blocks (CLBs)
- FF1696 Flip-Chip Fine-Pitch BGA Package
- 3-State Buffers
- FF1704 Flip-Chip Fine-Pitch BGA Package
- CLB/Slice Configurations
- 18-Kb Block SelectRAM Resources
- 18-Bit x 18-Bit Multipliers
- Global Clock Multiplexer Buffers
- Digital Clock Manager (DCM)
Routing
Configuration
IMPORTANT NOTE: Page, figure, and table numbers begin at 1 for each module, and each module has its own Revision
History at the end. Use the PDFBookmark pane for easy navigation in this volume.
20002011 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. PowerPC is
a trademark of IBM Corp. and is used under license. All other trademarks are the property of their respective owners.
DS083 (v5.0) June 21, 2011 www.xilinx.com 1
Product SpecificationProduct Not Recommended For New Designs
1
0
R Virtex-II Pro and Virtex-II Pro X Platform FPGAs:
Introduction and Overview
DS083 (v5.0) June 21, 2011 Product Specification
Summary of Virtex-II Pro / Virtex-II Pro X Features
High-Performance Platform FPGA Solution, Including - SelectRAM+ memory hierarchy
- Dedicated 18-bit x 18-bit multiplier blocks
- Up to twenty RocketIO or RocketIO X embedded
Multi-Gigabit Transceivers (MGTs) - High-performance clock management circuitry
- SelectI/O-Ultra technology
- Up to two IBM PowerPC RISC processor blocks
- XCITE Digitally Controlled Impedance (DCI) I/O
Based on Virtex-II Platform FPGA Technology
- Flexible logic resources
Virtex-II Pro / Virtex-II Pro X family members and resources
- SRAM-based in-system configuration
are shown in Table 1.
- Active Interconnect technology
Table 1: Virtex-II Pro / Virtex-II Pro X FPGA Family Members
CLB (1 = 4 slices =
max 128 bits) Block SelectRAM+
RocketIO PowerPC 18 X 18 Bit Maximum
Transceiver Processor Logic Max Distr Multiplier 18 Kb Max Block User
(1) (2)
Device Blocks Blocks Cells Slices RAM (Kb) Blocks Blocks RAM (Kb) DCMs I/O Pads
XC2VP2 4 0 3,168 1,408 44 12 12 216 4 204
XC2VP4 4 1 6,768 3,008 94 28 28 504 4 348
XC2VP7 8 1 11,088 4,928 154 44 44 792 4 396
XC2VP20 8 2 20,880 9,280 290 88 88 1,584 8 564
(4)
XC2VPX20 8 1 22,032 9,792 306 88 88 1,584 8 552
XC2VP30 8 2 30,816 13,696 428 136 136 2,448 8 644
(3)
XC2VP40 0 , 8, or 12 2 43,632 19,392 606 192 192 3,456 8 804
(3)
XC2VP50 0 or 16 2 53,136 23,616 738 232 232 4,176 8 852
XC2VP70 16 or 20 2 74,448 33,088 1,034 328 328 5,904 8 996
(4)
XC2VPX70 20 2 74,448 33,088 1,034 308 308 5,544 8 992
(3)
XC2VP100 0 or 20 2 99,216 44,096 1,378 444 444 7,992 12 1,164
Notes:
1. -7 speed grade devices are not available in Industrial grade.
2. Logic Cell (1) 4-input LUT + (1)FF + Carry Logic
3. These devices can be ordered in a configuration without RocketIO transceivers. See Table 3 for package configurations.
4. Virtex-II Pro X devices equipped with RocketIO X transceiver cores.
RocketIO X Transceiver Features (XC2VPX20 and XC2VPX70 Only)
Variable-Speed Full-Duplex Transceiver (XC2VPX20) Automatic Lock-to-Reference Function
Allowing 2.488 Gb/s to 6.25 Gb/s Baud Transfer Rates.
Programmable Serial Output Differential Swing
- Includes specific baud rates used by various
- 200 mV to 1600 mV, peak-peak
standards, as listed in Table 4, Module 2.
- Allows compatibility with other serial system
Fixed-Speed Full-Duplex Tranceiver (XC2VPX70)
voltage levels
Operating at 4.25 Gb/s Baud Transfer Rate.
Programmable Pre-emphasis Levels 0 to 500%
Eight or Twenty Transceiver Modules on an FPGA,
Telecom/Datacom Support Modes
Depending upon Device
-x8" andx10" clocking/data paths
Monolithic Clock Synthesis and Clock Recovery
- 64B/66B clocking support
- Eliminates the need for external components
20002011 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. PowerPC is
a trademark of IBM Corp. and is used under license. All other trademarks are the property of their respective owners.
DS083 (v5.0) June 21, 2011 www.xilinx.com Module 1 of 4
Product Specification 1