ICE40UL640-SWG16ITR1K Lattice

iCE40 UltraLite Family Data Sheet FPGA-DS-02027 Version 1.6 August 2018 iCE40 UltraLite Family Data Sheet Contents Acronyms in This Document ................................................................................................................................................. 5 1. General Description ...................................................................................................................................................... 6 1.1. Features ............................................................................................................................................................... 6 2. Product Family .............................................................................................................................................................. 7 2.1. Overview ............................................................................................................................................................. 7 3. Architecture .................................................................................................................................................................. 8 3.1. Architecture Overview ........................................................................................................................................ 8 3.1.1. PLB Blocks ....................................................................................................................................................... 9 3.1.1.1. Logic Cells ............................................................................................................................................... 9 3.1.2. Routing .......................................................................................................................................................... 10 3.1.3. Clock/Control Distribution Network ............................................................................................................. 10 3.1.3.1. Global Hi-Z Control ............................................................................................................................... 11 3.1.3.2. Global Reset Control ............................................................................................................................ 11 3.1.4. sysCLOCK Phase Locked Loops (PLLs) (sysCLOCK PLL is only supported in 36-ball ucBGA package) ............ 11 3.1.5. sysMEM Embedded Block RAM Memory ..................................................................................................... 12 3.1.5.1. sysMEM Memory Block ........................................................................................................................ 12 3.1.5.2. RAM Initialization and ROM Operation ................................................................................................ 13 3.1.5.3. Memory Cascading ............................................................................................................................... 13 3.1.5.4. RAM4K Block ........................................................................................................................................ 13 3.1.6. sysI/O Buffer Banks ....................................................................................................................................... 14 3.1.6.1. Programmable I/O (PIO) ....................................................................................................................... 14 3.1.6.2. Input Register Block ............................................................................................................................. 15 3.1.6.3. Output Register Block .......................................................................................................................... 15 3.1.7. sysI/O Buffer ................................................................................................................................................. 17 3.1.7.1. Typical I/O Behavior During Power-up ................................................................................................. 17 3.1.7.2. Supported Standards ............................................................................................................................ 17 3.1.7.3. Programmable Pull Up Resistors .......................................................................................................... 17 3.1.7.4. Differential Comparators ..................................................................................................................... 17 3.1.8. On-Chip Oscillator ......................................................................................................................................... 18 2 3.1.9. User I C IP ...................................................................................................................................................... 18 3.1.10. High Current LED Drive I/O Pins ............................................................................................................... 18 3.1.11. Hardened RGB PWM IP ............................................................................................................................ 19 3.1.12. Hardened IR Transceiver IP ...................................................................................................................... 19 3.1.13. Non-Volatile Configuration Memory ........................................................................................................ 19 3.1.14. Power On Reset ........................................................................................................................................ 19 3.2. iCE40 UltraLite Programming and Configuration .............................................................................................. 20 3.2.1. Device Programming ..................................................................................................................................... 20 3.2.2. Device Configuration ..................................................................................................................................... 20 3.2.3. Power Saving Options ................................................................................................................................... 20 4. DC and Switching Characteristics ................................................................................................................................ 21 4.1. Absolute Maximum Ratings .............................................................................................................................. 21 4.2. Recommended Operating Conditions ............................................................................................................... 21 4.3. Power Supply Ramp Rates ................................................................................................................................. 22 4.4. Power-On Reset ................................................................................................................................................ 22 4.5. Power-up Supply Sequence ............................................................................................................................... 22 4.6. External Reset.................................................................................................................................................... 22 4.7. Power-On-Reset Voltage Levels ........................................................................................................................ 23 4.8. ESD Performance ............................................................................................................................................... 24 4.9. DC Electrical Characteristics .............................................................................................................................. 24 4.10. Supply Current ................................................................................................................................................... 25 4.11. Internal Pull-Up Resistor Specifications ............................................................................................................ 25 2 4.12. User I C Specifications ....................................................................................................................................... 26 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 2 FPGA-DS-02027-1.6