1 Spartan-3 FPGA Family Data Sheet DS099 June 27, 2013 Product Specification Module 1: Module 4: Pinout Descriptions Introduction and Ordering Information DS099 (v3.1) June 27, 2013 DS099 (v3.1) June 27, 2013 Pin Descriptions Introduction Pin Behavior During Configuration Features Package Overview Architectural Overview Pinout Tables Array Sizes and Resources Footprints User I/O Chart Ordering Information Module 2: Functional Description DS099 (v3.1) June 27, 2013 Input/Output Blocks (IOBs) IOB Overview SelectIO Interface I/O Standards Configurable Logic Blocks (CLBs) Block RAM Dedicated Multipliers Digital Clock Manager (DCM) Clock Network Configuration Module 3: DC and Switching Characteristics DS099 (v3.1) June 27, 2013 DC Electrical Characteristics Absolute Maximum Ratings Supply Voltage Specifications Recommended Operating Conditions DC Characteristics Switching Characteristics I/O Timing Internal Logic Timing DCM Timing Configuration and JTAG Timing Copyright 20032013 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, Artix, Kintex, Zynq, Vivado, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners. DS099 June 27, 2013 www.xilinx.com Product Specification 18 Spartan-3 FPGA Family: Introduction and Ordering Information DS099 (v3.1) June 27, 2013 Product Specification Introduction Features Low-cost, high-performance logic solution for high-volume, The Spartan-3 family of Field-Programmable Gate Arrays consumer-oriented applications is specifically designed to meet the needs of high volume, Densities up to 74,880 logic cells cost-sensitive consumer electronic applications. The SelectIO interface signaling Up to 633 I/O pins eight-member family offers densities ranging from 50,000 to 622+ Mb/s data transfer rate per I/O 5,000,000 system gates, as shown in Table 1. 18 single-ended signal standards 8 differential I/O standards including LVDS, RSDS The Spartan-3 family builds on the success of the earlier Termination by Digitally Controlled Impedance Spartan-IIE family by increasing the amount of logic Signal swing ranging from 1.14V to 3.465V resources, the capacity of internal RAM, the total number of Double Data Rate (DDR) support I/Os, and the overall level of performance as well as by DDR, DDR2 SDRAM support up to 333 Mb/s improving clock management functions. Numerous Logic resources Abundant logic cells with shift register capability enhancements derive from the Virtex-II platform Wide, fast multiplexers technology. These Spartan-3 FPGA enhancements, Fast look-ahead carry logic combined with advanced process technology, deliver more Dedicated 18 x 18 multipliers functionality and bandwidth per dollar than was previously JTAG logic compatible with IEEE 1149.1/1532 possible, setting new standards in the programmable logic SelectRAM hierarchical memory Up to 1,872 Kbits of total block RAM industry. Up to 520 Kbits of total distributed RAM Because of their exceptionally low cost, Spartan-3 FPGAs Digital Clock Manager (up to four DCMs) Clock skew elimination are ideally suited to a wide range of consumer electronics Frequency synthesis applications, including broadband access, home High resolution phase shifting networking, display/projection and digital television Eight global clock lines and abundant routing equipment. Fully supported by Xilinx ISE and WebPACK software The Spartan-3 family is a superior alternative to mask development systems programmed ASICs. FPGAs avoid the high initial cost, the MicroBlaze and PicoBlaze processor, PCI, PCI Express PIPE Endpoint, and other IP cores lengthy development cycles, and the inherent inflexibility of Pb-free packaging options conventional ASICs. Also, FPGA programmability permits Automotive Spartan-3 XA Family variant design upgrades in the field with no hardware replacement necessary, an impossibility with ASICs. Table 1: Summary of Spartan-3 FPGA Attributes CLB Array Distributed Block Maximum (One CLB = Four Slices) System Equivalent Dedicated Max. Device RAM Bits RAM Bits DCMs Differential (1) Gates Logic Cells Multipliers User I/O Total (K=1024) (K=1024) I/O Pairs Rows Columns CLBs (2) XC3S50 50K 1,728 16 12 192 12K 72K 4 2 124 56 (2) XC3S200 200K 4,320 24 20 480 30K 216K 12 4 173 76 (2) XC3S400 400K 8,064 32 28 896 56K 288K 16 4 264 116 (2) XC3S1000 1M 17,280 48 40 1,920 120K 432K 24 4 391 175 XC3S1500 1.5M 29,952 64 52 3,328 208K 576K 32 4 487 221 XC3S2000 2M 46,080 80 64 5,120 320K 720K 40 4 565 270 XC3S4000 4M 62,208 96 72 6,912 432K 1,728K 96 4 633 300 XC3S5000 5M 74,880 104 80 8,320 520K 1,872K 104 4 633 300 Notes: 1. Logic Cell = 4-input Look-Up Table (LUT) plus a D flip-flop.Equivalent Logic Cell equalsTotal CLB x 8 Logic Cells/CLB x 1.125 effectiveness. 2. These devices are available in Xilinx Automotive versions as described in DS314: Spartan-3 Automotive XA FPGA Family. Copyright 20032013 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, Artix, Kintex, Zynq, Vivado, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners. DS099 (v3.1) June 27, 2013 www.xilinx.com Product Specification 2