18 7 Series FPGAs Data Sheet: Overview DS180 (v2.5) August 1, 2017 Product Specification General Description Xilinx 7 series FPGAs comprise four FPGA families that address the complete range of system requirements, ranging from low cost, small form factor, cost-sensitive, high-volume applications to ultra high-end connectivity bandwidth, logic capacity, and signal processing capability for the most demanding high-performance applications. The 7 series FPGAs include: Spartan-7 Family: Optimized for low cost, lowest power, and high Kintex-7 Family: Optimized for best price-performance with a 2X I/O performance. Available in low-cost, very small form-factor improvement compared to previous generation, enabling a new class packaging for smallest PCB footprint. of FPGAs. Artix-7 Family: Optimized for low power applications requiring serial Virtex-7 Family: Optimized for highest system performance and transceivers and high DSP and logic throughput. Provides the lowest capacity with a 2X improvement in system performance. Highest total bill of materials cost for high-throughput, cost-sensitive capability devices enabled by stacked silicon interconnect (SSI) applications. technology. Built on a state-of-the-art, high-performance, low-power (HPL), 28 nm, high-k metal gate (HKMG) process technology, 7 series FPGAs enable an unparalleled increase in system performance with 2.9 Tb/s of I/O bandwidth, 2 million logic cell capacity, and 5.3 TMAC/s DSP, while consuming 50% less power than previous generation devices to offer a fully programmable alternative to ASSPs and ASICs. Summary of 7 Series FPGA Features Advanced high-performance FPGA logic based on real 6-input look- Powerful clock management tiles (CMT), combining phase-locked up table (LUT) technology configurable as distributed memory. loop (PLL) and mixed-mode clock manager (MMCM) blocks for high precision and low jitter. 36 Kb dual-port block RAM with built-in FIFO logic for on-chip data buffering. Integrated block for PCI Express (PCIe), for up to x8 Gen3 Endpoint and Root Port designs. High-performance SelectIO technology with support for DDR3 interfaces up to 1,866 Mb/s. Wide variety of configuration options, including support for commodity memories, 256-bit AES encryption with HMAC/SHA-256 High-speed serial connectivity with built-in multi-gigabit transceivers authentication, and built-in SEU detection and correction. from 600 Mb/s to maximum rates of 6.6 Gb/s up to 28.05 Gb/s, offering a special low-power mode, optimized for chip-to-chip Low-cost, wire-bond, lidless flip-chip, and high signal integrity flip- interfaces. chip packaging offering easy migration between family members in the same package. All packages available in Pb-free and selected A user configurable analog interface (XADC), incorporating dual packages in Pb option. 12-bit 1MSPS analog-to-digital converters with on-chip thermal and supply sensors. Designed for high performance and lowest power with 28 nm, HKMG, HPL process, 1.0V core voltage process technology and DSP slices with 25 x 18 multiplier, 48-bit accumulator, and pre-adder 0.9V core voltage option for even lower power. for high-performance filtering, including optimized symmetric coefficient filtering. Table 1: 7 Series Families Comparison Max. Capability Spartan-7 Artix-7 Kintex-7 Virtex-7 Logic Cells 102K 215K 478K 1,955K (1) Block RAM 4.2Mb 13Mb 34Mb 68Mb DSP Slices 160 740 1,920 3,600 (2) DSP Performance 176 GMAC/s 929 GMAC/s 2,845 GMAC/s 5,335 GMAC/s Transceivers 16 32 96 Transceiver Speed 6.6 Gb/s 12.5 Gb/s 28.05 Gb/s Serial Bandwidth 211 Gb/s 800 Gb/s 2,784 Gb/s PCIe Interface x4 Gen2 x8 Gen2 x8 Gen3 Memory Interface 800 Mb/s 1,066 Mb/s 1,866 Mb/s 1,866 Mb/s I/O Pins 400 500 500 1,200 I/O Voltage 1.2V3.3V 1.2V3.3V 1.2V3.3V 1.2V3.3V Package Options Low-Cost, Wire-Bond, Lidless Lidless Flip-Chip and High- Highest Performance Low-Cost, Wire-Bond Flip-Chip Performance Flip-Chip Flip-Chip Notes: 1. Additional memory available in the form of distributed RAM. 2. Peak DSP performance numbers are based on symmetrical filter implementation. Copyright 20102017 Xilinx, Inc., Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI Express is a trademark of PCI-SIG and used under license. All other trademarks are the property of their respective owners. DS180 (v2.5) August 1, 2017 www.xilinx.com Product Specification 17 Series FPGAs Data Sheet: Overview Spartan-7 FPGA Feature Summary Table 2: Spartan-7 FPGA Feature Summary by Device (3) CLB Block RAM Blocks Logic DSP XADC Total I/O Max User (4) Device Max CMTs PCIe GT (2) (5) Cells Slices Max Blocks Banks I/O (1) Slices Distributed 18 Kb 36 Kb (Kb) RAM (Kb) XC7S6 6,000 938 70 10 10 5 180 2 0 0 0 2 100 XC7S15 12,800 2,000 150 20 20 10 360 2 0 0 0 2 100 XC7S25 23,360 3,650 313 80 90 45 1,620 3 0 0 1 3 150 XC7S50 52,160 8,150 600 120 150 75 2,700 5 0 0 1 5 250 XC7S75 76,800 12,000 832 140 180 90 3,240 8 0 0 1 8 400 XC7S100 102,400 16,000 1,100 160 240 120 4,320 8 0 0 1 8 400 Notes: 1. Each 7 series FPGA slice contains four LUTs and eight flip-flops only some slices can use their LUTs as distributed RAM or SRLs. 2. Each DSP slice contains a pre-adder, a 25 x 18 multiplier, an adder, and an accumulator. 3. Block RAMs are fundamentally 36 Kb in size each block can also be used as two independent 18 Kb blocks. 4. Each CMT contains one MMCM and one PLL. 5. Does not include configuration Bank 0. Table 3: Spartan-7 FPGA Device-Package Combinations and Maximum I/Os Package CPGA196 CSGA225 CSGA324 FTGB196 FGGA484 FGGA676 Size (mm) 8 x 8 13 x 13 15 x 15 15 x 15 23 x 23 27 x 27 Ball Pitch (mm) 0.50.8 0.81.0 1.01.0 (1) (1) (1) (1) (1) (1) Device HR I/O HR I/O HR I/O HR I/O HR I/O HR I/O XC7S6 100 100 100 XC7S15 100 100 100 XC7S25 150 150 100 XC7S50 210 100 250 XC7S75 338 400 XC7S100 338 400 Notes: 1. HR = High-range I/O with support for I/O voltage from 1.2V to 3.3V. DS180 (v2.5) August 1, 2017 www.xilinx.com Product Specification 2