0 R XC95288XL High Performance CPLD 05 DS055 (v2.1 April 3, 2007 Product Specification cations and computing systems. It is comprised of 16 Features 54V18 Function Blocks, providing 6,400 usable gates with 6 ns pin-to-pin logic delays propagation delays of 6 ns. See Figure 2 for architecture System frequency up to 208 MHz overview. 288 macrocells with 6,400 usable gates Available in small footprint packages Power Estimation - 144-pin TQFP (117 user I/O pins) Power dissipation in CPLDs can vary substantially depend- - 208-pin PQFP (168 user I/O pins) ing on the system frequency, design application and output - 256-pin BGA (192 user I/O pins) loading. To help reduce power dissipation, each macrocell - 256-pin FBGA (192 user I/O pins) in a XC9500XL device may be configured for low-power - 280-pin CSP (192 user I/O pins) mode (from the default high-performance mode). In addi- tion, unused product-terms and macrocells are automati- - Pb-free available for all packages cally deactivated by the software to further conserve power. Optimized for high-performance 3.3V systems - Low power operation For a general estimate of I , the following equation may be CC - 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V used: signals I (mA) = MC (0.175*PT + 0.345) + MC (0.052*PT CC HS HS LP LP - 3.3V or 2.5V output capability + 0.272) + 0.04 * MC (MC +MC )* f TOG HS LP - Advanced 0.35 micron feature size CMOS where: Fast FLASH technology MC = macrocells in high-speed configuration HS Advanced system features PT = average number of high-speed product terms HS - In-system programmable per macrocell - Superior pin-locking and routability with MC = macrocells in low power configuration LP Fast CONNECT II switch matrix PT = average number of low power product terms per LP - Extra wide 54-input Function Blocks macrocell - Up to 90 product-terms per macrocell with f = maximum clock frequency individual product-term allocation MCTOG = average % of flip-flops toggling per clock - Local clock inversion with three global and one (~12%) product-term clocks This calculation was derived from laboratory measurements of an XC9500XL part filled with 16-bit counters and allowing - Individual output enable per output pin with local a single output (the LSB) to be enabled. The actual I inversion CC value varies with the design application and should be veri- - Input hysteresis on all user and boundary-scan pin fied during normal system operation. Figure 1 shows the inputs above estimation in a graphical form. For a more detailed - Bus-hold circuitry on all user pin inputs discussion of power consumption in this device, see Xilinx - Full IEEE Standard 1149.1 boundary-scan (JTAG) Fast concurrent programming Slew rate control on individual outputs Enhanced data security features Excellent quality and reliability - Endurance exceeding 10,000 program/erase cycles - 20 year data retention - ESD protection exceeding 2,000V Pin-compatible with 5V-core XC95288 device in the 208-pin HQFP package WARNING: Programming temperature range of T = 0 C to +70 C A Description The XC95288XL is a 3.3V CPLD targeted for high-perfor- mance, low-voltage applications in leading-edge communi- 1998-2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at R XC95288XL High Performance CPLD application note XAPP114, Understanding XC9500XL CPLD Power. 550 208 MHz 500 450 400 350 300 250 94 MHz 200 150 100 50 0 100 200 250 50 150 Clock Frequency (MHz) DS055 01 121501 Figure 1: Typical I vs. Frequency for XC95288XL CC 2 www.xilinx.com DS055 (v2.1 April 3, 2007 1-800-255-7778 Product Specification Hi rformanc ghPe e LowPower Typical I (mA) CC