Product Obsolete/Under Obsolescence 0 R Spartan and Spartan-XL FPGA Families Data Sheet 00 DS060 (v2.0) March 1, 2013 Product Specification System level features Introduction - Available in both 5V and 3.3V versions The Spartan and the Spartan-XL FPGA families are a - On-chip SelectRAM memory high-volume production FPGA solution that delivers all the - Fully PCI compliant key requirements for ASIC replacement up to 40,000 gates. - Full readback capability for program verification These requirements include high performance, on-chip and internal node observability RAM, core solutions and prices that, in high volume, - Dedicated high-speed carry logic approach and in many cases are equivalent to mask pro- - Internal 3-state bus capability grammed ASIC devices. - Eight global low-skew clock or signal networks By streamlining the Spartan series feature set, leveraging - IEEE 1149.1-compatible Boundary Scan logic advanced process technologies and focusing on total cost - Low cost plastic packages available in all densities management, the Spartan series delivers the key features - Footprint compatibility in common packages required by ASIC and other high-volume logic users while avoiding the initial cost, long development cycles and inher- Fully supported by powerful Xilinx ISE Classics ent risk of conventional ASICs. The Spartan and Spar- development system tan-XL families in the Spartan series have ten members, as - Fully automatic mapping, placement and routing shown in Table 1. Additional Spartan-XL Family Features Spartan/Spartan-XL FPGA Features 3.3V supply for low power with 5V tolerant I/Os Power down input Note: The Spartan series devices described in this data sheet include the 5V Spartan family and the 3.3V Higher performance Spartan-XL family. See the separate data sheets for more Faster carry logic advanced members for the Spartan Series. More flexible high-speed clock network First ASIC replacement FPGA for high-volume Latch capability in Configurable Logic Blocks production with on-chip RAM Input fast capture latch Density up to 1862 logic cells or 40,000 system gates Optional MUX or 2-input function generator on outputs Streamlined feature set based on XC4000 architecture 12 mA or 24 mA output drive System performance beyond 80 MHz 5V and 3.3V PCI compliant Broad set of AllianceCORE and LogiCORE Enhanced Boundary Scan predefined solutions available Express Mode configuration Unlimited reprogrammability Low cost Table 1: Spartan and Spartan-XL Field Programmable Gate Arrays Max Typical Max. Total Logic System Gate Range CLB Total No. of Avail. Distributed (1) Device Cells Gates (Logic and RAM) Matrix CLBs Flip-flops User I/O RAM Bits XCS05 and XCS05XL 238 5,000 2,000-5,000 10 x 10 100 360 77 3,200 XCS10 and XCS10XL 466 10,000 3,000-10,000 14 x 14 196 616 112 6,272 XCS20 and XCS20XL 950 20,000 7,000-20,000 20 x 20 400 1,120 160 12,800 XCS30 and XCS30XL 1368 30,000 10,000-30,000 24 x 24 576 1,536 192 18,432 (2) XCS40 and XCS40XL 1862 40,000 13,000-40,000 28 x 28 784 2,016 205 25,088 Notes: 1. Max values of Typical Gate Range include 20-30% of CLBs used as RAM. 2. XCS40XL provided 224 max I/O in CS280 package discontinued by PDN2004-01. 1998-2013 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at Product Obsolete/Under Obsolescence R Spartan and Spartan-XL FPGA Families Data Sheet memory cells determine the logic functions and intercon- General Overview nections implemented in the FPGA. The FPGA can either Spartan series FPGAs are implemented with a regular, flex- actively read its configuration data from an external serial ible, programmable architecture of Configurable Logic PROM (Master Serial mode), or the configuration data can Blocks (CLBs), interconnected by a powerful hierarchy of be written into the FPGA from an external device (Slave versatile routing resources (routing channels), and sur- Serial mode). rounded by a perimeter of programmable Input/Output Spartan series FPGAs can be used where hardware must Blocks (IOBs), as seen in Figure 1. They have generous be adapted to different user applications. FPGAs are ideal routing resources to accommodate the most complex inter- for shortening design and development cycles, and also connect patterns. offer a cost-effective solution for production rates well The devices are customized by loading configuration data beyond 50,000 systems per month. into internal static memory cells. Re-programming is possi- ble an unlimited number of times. The values stored in these B- OSC SCAN IOB IOB CLB CLB CLB CLB IOB IOB IOB IOB CLB CLB CLB CLB IOB IOB Routing Channels IOB IOB CLB CLB CLB CLB IOB IOB IOB IOB CLB CLB CLB CLB IOB IOB START RDBK -UP VersaRing Routing Channels DS060 01 081100 Figure 1: Basic FPGA Block Diagram 2 www.xilinx.com DS060 (v2.0) March 1, 2013 Product Specification IOB IOB IOB IOB IOB IOB IOB IOB IOB IOB IOB IOB IOB IOB IOB IOB