eZ80 Microprocessors
eZ80L92 Product Brief
PB008607-0103
Real-time clock with on-chip 32KHz oscillator,
Product Block Diagram
selectable 50/60Hz input, and separate V pin
DD
for battery backup
eZ80L92 MPU
JTAG Debug Interface (also supports ZiLOG
Debug Interface)
Infrared
New DMA-like eZ80 instructions
24-Bit GPIO Encoder/ 2 UART
Decoder
Power management features including SLEEP/
HALT modes and peripheral power-down con-
2
I C SPI 6 PRT WDT
trols
100-pin LQFP package
Real-
4 CS +
3.03.6V supply voltage with 5V tolerant inputs
JTAG ZDI
Time
WSG
Operating Temperature Ranges:
Clock
Standard: 0C to +70C
Extended: 40C to +105C
Features
General Description
The eZ80L92 microprocessor is a member of
ZiLOGs eZ80 product family. It offers the fol-
The eZ80L92 is a power-efcient, optimized pipe-
lowing features:
line architecture microprocessor operating up to
50 MHz. It is part of a line of eZ80 -based standard
High-performance, pipelined eZ80 CPU avail-
products targeted toward industrial, communica-
able at 20MHz or 50MHz maximum speed
tion, security, automation, and embedded Internet
24 bits of General-Purpose I/O
applications.
IrDA compatible Infrared Encoder/Decoder
2 UARTs with independent baud rate generators
eZ80 CPU Core
2
I C with independent clock rate generator
The eZ80 can operate in Z80-compatible (64KB)
SPI with independent clock rate generator
mode or full 24-bit (16 MB) addressing mode.
Glueless external memory interface with 4 Chip
Considering both the increased clock speed and
Selects, independent WAIT state generators, and
processor efciency, the eZ80 s processing power
external WAIT input pin; supports Z80, Intel,
rivals the performance of 16-bit microprocessors.
and Motorola bus-compatible peripherals.
The eZ80 improves on the world-famous Z80
Six 16-bit Counter/Timers with prescalers and
architecture. Like the Z80, it features dual bank
direct input/output drive capability
registers for fast context switching.
Interrupt controller supports internal and exter-
nal maskable interrupts as well as a non- eZ80L92 Peripherals
maskable interrupt input
General-Purpose Input/Output
Watch-Dog Timer
The eZ80L92 microprocessor features 24 bits of
General-Purpose Input or Output (GPIO). All port
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eZ80L92 Product Brief
2
signals are programmable in Input or Output CLK 64, and CLK 256. The timers two modes
modes. The 24 port bits can be used as vectored of operation are single-pass and continuous count
interrupt sources. The pins can be set to recognize mode. Four timers can be driven through a GPIO
either level- or edge-triggered interrupts. input pin for external event count. Two others
allow the ability to drive their outputs through
Infrared Encoder/Decoder
GPIO pins.
Supports IrDA SIR format
Watch-Dog Timer
Operates seamlessly with the on-chip UART
The Watch-Dog Timer (WDT) features four pro-
Interfaces with IrDA -compliant transceivers
grammable time-out periods: 218, 222, 225, or 227
Supports transmit/receive up to 115.2kbps
clock cycles. It allows the user to monitor the sta-
Universal Asynchronous Receiver/
tus of a time-out and generate a RESET or non-
Transmitters
maskable interrupt. The WDT can operate from
Each of the two Universal Asynchronous Receiver/ either the system clock or the on-chip 32 KHz
Transmitters (UART) devices contains control reg- oscillator used by the RTC.
isters and a Baud Rate Generator (BRG).
Real-Time Clock
The Baud Rate Generator produces a lower-fre-
The real-time clock (RTC) allows counting of sec-
quency bit clock from the system clock. All
onds, minutes, hours, days-of-the-week, day-of-
standard baud rates up to 115kbps and some
the-month, month, year, and century. Alarms and
rates higher than 115kbps are supported.
interrupts can be set for seconds, minutes, hours,
The UART module implements all the logic
and day-of-the-week. The real-time clock input can
required to support asynchronous communica-
be taken from the on-chip 32 KHz oscillator or
tions and hardware ow control. The module
from a 50/60 Hz input. The real-time clock oper-
also contains separate 16-byte-deep transmit
ates from an isolated V pin to allow constant
DD
and receive FIFOs.
operation from a battery.
Inter-Integrated Circuit
Chip Select/Wait State Generator
2
The Inter-Integrated Circuit (I C) device contains
and WAIT Pin
control registers and its own clock rate generator.
There are four chip selects for external devices.
2
The I C operates in four modes: Master Transmit
Each chip select may be programmed for either
or Receive, Slave Transmit or Receive.
memory or I/O space. Each memory chip select can
Serial Peripheral Interface be individually programmed on a 64KB boundary.
The I/O chip selects can choose a 256-byte section
The Serial Peripheral Interface (SPI) device con-
of I/O space. The WAIT input pin allows interface
tains control registers and its own clock rate gener-
with slow peripherals. The chip selects support
ator. The SPI is a synchronous interface allowing
Z80-, Intel-, and Motorola-style buses.
several SPI-type devices to be interconnected. The
SPI may be congured as either a master or a slave.
JTAG Debug Interface
Programmable Reload Timers The IEEE1149.1-compatible JTAG interface sup-
ports all of the ZDI functions plus the following
The eZ80L92 features six Programmable Reload-
features: software break points, 64-word trace
able Counter Timers (PRT). Each timer is a 16-bit
buffer, complex break points using address and
down counter and offers a 4-bit clock prescaler
data masks, and cascadable triggers.
with four selectable taps for CLK 4, CLK 16,
PB008607-0103 eZ80 Microprocessors