PRELIMINARY ZILOG Z16C32 IUSC PRELIMINARY PRODUCT SPECIFICATION Z16C32 IUSC INTEGRATED UNIVERSAL SERIAL CONTROLLER FEATURES Two Full-Capacity 20 MHz DMA Channels, Each with HDLC/SDLC Mode with 8-Bit Address Compare 32-Bit Addressing and 16-Bit Data Transfers. Extended Address Field Option 16- or 32-Bit CRC Programmable Idle Line Condition Optional Preamble DMA Modes Include Single Buffer, Pipelined, Array- Transmission and Loop Mode. Selectable Number of Chained and Linked-Array Chained. Flags Between Back-to-Back Frames. Ring Buffer Feature Supports Circular Queue of Buffers Byte Oriented Synchronous Mode with One-to-Eight in Memory. Bits/Character Programmable Sync and Idle Line Conditions Optional Receive Sync Stripping Optional Linked Frame Status Transfer Feature Writes Status Preamble Transmission 16- or 32-Bit CRC Transmit- Information for Received Frames and Reads Control to-Receive Slaving (for X.21). Information for Transmit Frames to the DMA Channels Array or Linked List to Significantly Simplify Processing External Character Sync Mode for Receive Frame Status and Control Information. Transparent Bisync Mode with EBCDIC or ASCII Programmable Throttling of DMA Bus Occupancy in Character Code Automatic CRC Handling Burst Mode with Bus Occupancy Time Limitation. Programmable Idle Line Condition Optional Preamble Transmission Automatic Recognition of DLE, SYN, 0 to 20 Mbit/sec, Full-Duplex Channel, with Two Baud SOH, ITX, ETX, ETB, EOT, ENQ and ITB. Rate Generators and a Digital Phase-Locked Loop for Clock Recovery. Flexible Bus Interface for Direct Connection to Most Microprocessors User Programmable for 8 or 16 Bits 32-Byte Data FIFOs for Receiver and Transmitter Wide. Directly Supports 680X0 Family or 8X86 Family Bus Interfaces. Up to 12.5 MByte/sec (16-Bit) Data Bus Bandwidth Receive and Transmit Time Slot Assigners for ISDN, Multiprotocol Operation Under Program Control with T1 and E1 (CEPT) Applications. Independent Mode Selection for Receiver and Transmitter. 8-Bit General-Purpose Port with Transition Detection Async Mode with One-to-Eight Bits/Character, 1/16 to Low Power CMOS Two Stop Bits/Character in 1/16 Bit Increments 16x, 32x, or 64x Oversampling Break Detect and 68-Pin PLCC Package Generation Odd, Even, Mark, Space or No Parity and Framing Error Detection. Supports 9-Bit and MIL-STD- Electronic Programmer s Manual Support Tool and 1553B Protocols. Software Drivers are Available. GENERAL DESCRIPTION The Z16C32 IUSC (Integrated Universal Serial Controller) serial communications channel with high-performance is a multiprotocol datacommunications device with on- DMA facilitates higher data throughput than can be chip dual-channel DMA. The integration of a high-speed achieved with discrete serial/DMA chip combinations. 1 PS97USC0200 PRELIMINARY ZILOG Z16C32 IUSC GENERAL DESCRIPTION (Continued) There are additional reasons for using the Z16C32 IUSC data without separate address to support multiplexed or than just reduced chip count and board space economy. non-multiplexed busses. The DMA and serial channel intercommunication offers application benefits as well. For example, events such as The IUSC handles asynchronous formats, synchronous the reception of the end of a HDLC frame is internally bit-oriented formats such as HDLC and synchronous byte- communicated from the serial controller to the DMA so that oriented formats (e.g., BISYNC and DDCMP). This device each frame can be written into a separate memory buffer. supports virtually any serial data transfer application. The buffer chaining capabilities, ring buffer support, auto- mated frame status/control blocks, and buffer termination The IUSC can generate and check CRC in any synchro- at the end of the frame combine to significantly reduce nous mode. Complete access to the CRC value allows CPU overhead (Figure 1). system software to resend or manipulate the CRC as needed in various applications. The IUSC also provides The IUSC is software configurable to satisfy a wide variety facilities for modem control signals. In applications where of serial communication applications. The 20 Mbit/second these controls are not needed, the modem controls can be data rate and multiple protocol support make it ideal for used for general-purpose I/O. applications in todays dynamic environment of changing specifications and increasing speed. The many program- Interrupts are supported by a daisy-chain hierarchy within mable features allow the user to tune the device response the serial channel and between the serial channel and the to meet system requirements and adapt to future require- DMA. Separate interrupt vectors for each type of interrupt ments. The IUSC contains a variety of sophisticated inter- within the serial controller and the DMA facilitate fast nal functions including two baud rate generators, a digital discrimination of the interrupt source. The IUSC supports phase-locked loop, character counters, and 32-byte FIFOs Pulsed, Double Pulsed, and Status Interrupt Acknowledge for both the receiver and the transmitter. cycles. The on-chip DMA channels allow high speed data trans- Support tools are available to aid the designer in efficiently fers for both the receiver and the transmitter. The IUSC programming the IUSC. The Technical Manual describes supports automatic status and control transfer through in detail all the features and gives programming sequence DMA and allows initialization of the serial controller under hints. The Electronic Programmer s Manual, DC 8287-02, DMA control. Each DMA channel can do a 16-bit transfer is an MS-DOS, disk-based programming initialization tool in as little as three 50 ns clock cycles and can generate that can generate custom sequences. Also, Zilog offers addresses compatible with 32-, 24- or 16-bit memory assorted application notes and development boards to ranges. The DMA channels operate in any of four modes: assist the designer in hardware and software develop- single buffer, pipelined, array-chained, or linked-list. The ment. Contact your nearest Zilog representative for addi- array-chained and linked-list modes provide scatter-read tional information. and gather-write capabilities with minimal software inter- Notes: vention. To prevent the DMA from holding bus mastership All Signals with a preceding front slash,, are active Low, e.g.: too long, mastership time may be limited by counting the B//W (WORD is active Low) /B/W (BYTE is active Low, only). absolute number of clock cycles, the number of bus transactions, or both. Power connections follow conventional descriptions below: The CPU bus interface is designed for use with any Connection Circuit Device conventional multiplexed or non-multiplexed bus from Power V V CC DD manufacturers of CISC and RISC processors including Ground GND V SS Intel, Motorola, and Zilog. The bus interface is configurable for 16-bit data, 8-bit data with separate address or 8-bit 2 PS97USC0200