Z8018233ASG ZiLOG

Z80182/Z8L182 Zilog ZILOG INTELLIGENT PERIPHERAL PRELIMINARY PRELIMINARY PRODUCT SPECIFICATION Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP ) FEATURES n Z8S180 MPU n Two ESCC Channels with 32-Bit CRC - Code Compatible with Zilog Z80 /Z180 CPU - Extended Instructions n Three 8-Bit Parallel I/O Ports - Operating Frequency: 33 MHz/5V or 20 MHz/3.3V - Two DMA Channels n 16550 Compatible MIMIC Interface for - On-Chip Wait State Generators Direct Connection to PC, XT, AT Bus - Two UART Channels - Two 16-Bit Timer Counters n 100-Pin Package Styles (QFP, VQFP) - On-Chip Interrupt Controller (0.8 Micron CMOS 5120 Technology) - On-Chip Clock Oscillator/Generator - Clocked Serial I/O Port n Individual WSG for RAMCS and ROMCS - Fully Static - Low EMI Option GENERAL DESCRIPTION The Z80182/Z8L182 is a smart peripheral controller IC for error correction on outgoing and incoming data. In external modem (in particular V. Fast applications), fax, voice applications, three 8-bit parallel ports are available for messaging and other communications applications. It driving LEDs or other devices. Figure 1 shows the Z80182/ uses the Z80180 microprocessor (Z8S180 MPU core) Z8L182 block diagram, while the pin assignments for the linked with two channels of the industry standard Z85230 QFP and the VQFP packages are shown in Figures 2 and ESCC (Enhanced Serial Communications Controller), 24 3, respectively. All references in this document to the bits of parallel I/O, and a 16550 MIMIC for direct connection Z80182, or Z182 refer to both the Z80182 and Z8L182. to the IBM PC, XT, AT bus. Notes: All Signals with a preceding front slash,, are active Low, e.g., The Z80182/Z8L182 allows complete flexibility for both B//W (WORD is active Low) /B/W (BYTE is active Low, only). internal PC and external applications. Also current PC modem software compatibility can be maintained with the Power connections follow conventional descriptions below: Z80182/Z8L182 ability to mimic the 16550 UART chip. The Z80180 acts as an interface between the ESCC and Connection Circuit Device 16550 MIMIC interface when used in internal applications, Power V V and between the two ESCC channels in the external CC DD Ground GND V applications. This interface allows data compression and SS DS971820600 3-1Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL Zilog PRELIMINARY GENERAL DESCRIPTION (Continued) D7-D0 EV1 Control GLU Logic A19-A0 EV2 Bus Transceiver Z8S180 Tx Data (Static Z80180) MPU Core 85230 85230 ESCC ESCC Rx Data Channel Channel A B ESCC /TRxCB Control 16550 /ROMCS Address MIMIC Decode /RAMCS Interface 8-Bit Parallel 8-Bit Parallel 8-Bit Parallel Port C Port B Port A MUX MUX MUX 85230 ESCC Ch. A 16550 MIMIC or Port C or ESCC 85230 Ch. B and Port A Z180 Signals or Port B Note: Conventional use of the termMPU sid refers to all interface through the Z180 MPU core andPC sid refers to all interface through the16550 MIMIC interface. Figure 1. Z80182/Z8L182 Functional Block Diagram 3-2 DS971820600