PRODUCT SPECIFICATION Z89223/273/323/373 16-BIT DIGITAL SIGNAL PROCESSORS WITH A/D CONVERTER FEATURES ROM OTP Data RAM Device Package (Kwords) (Kwords) (Words) MIPS Z89223 44-PLCC, 44-PQFP 8 512 20 Z89273 44-PLCC 8 512 20 Z89323 64-TQFP, 68-PLCC, 80-PQFP 8 512 20 Z89373 64-TQFP, 68-PLCC, 80-PQFP 8 512 20 Operating Range On-Chip Peripherals 5V 10% 4-Channel, 8-Bit Half-Flash A/D Converter 0C to 70C Standard Temperature Serial Peripheral Interface (SPI) 40C to +85C Extended Temperature Three General-Purpose Counter/Timers Two Pulse Width Modulators (PWM) DSP Core Two Watch-Dog Timers (WDT) 16-Bit Fixed Point DSP, 24-Bit ALU and Accumulator Up to 40 Bits of I/O Single-Cycle Multiply and ALU Operations PLL System Clock Six-Level Hardware Stack Three Vectored Interrupts Servicing Eight Sources Six Data RAM Pointers and Sixteen Program Memory Pointers Low Power Clock Modes with Wake-up Options RISC Processor with 30 Instruction Types GENERAL DESCRIPTION The Z893x3 products are high-performance Digital Signal Six data RAM pointers provide circular buffer capabilities Processors (DSP) with a modified Harvard architecture fea- and simultaneous dual operand fetching. Three vectored in- turing separate program and dual data memory banks. The terrupts are complemented by a six-level stack. design is optimized for processing power with a minimum By integrating a high-speed 4-channel, 8-bit A/D, SPI, three of silicon area. Counter/Timers with PWM and WDT support, and up to 40 The Z893x3 16/24-Bit architecture accommodates ad- bits of I/O, the Z893x3 family provides a compact low-cost vanced signal processing algorithms. The operating perfor- system solution. mance and efficient architecture provide deterministic in- To support a wide variety of development requirements, the struction execution. Compression, filtering, frequency Z893x3 DSP product family features the cost-effective detection, audio, voice detection, speech synthesis, and oth- Z89223/323 with 8 KWords of ROM. The Z89273/373, an er vital algorithms can all be implemented. DS000202-DSP0599 1 Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter ZiLOG GENERAL DESCRIPTION (Continued) OTP version of the Z89223/323, is ideal for prototypes and early production builds. Notes: All signals with an overline are active Low. For example, in RD/WR, RD is active High and WR is Throughout this specification, references to the Z893x3 de- active Low. For I/O ports, P1.3 denotes Port1 bit 3. Pins vice apply equally to the Z89223/273/323/373, unless oth- called NC are No Connectionthey do not connect erwise specified. any power, grounds, or signals. Power connections follow conventional descriptions: Connection Circuit Device Power V V CC DD Ground GND V SS Program Data RAM0 Data RAM1 ROM/OTP 256x16 256x16 Port 0 8192x16 D0:03:0 D0:13:1 EA2EA0 ED15ED0 8 8 DS 16-Bit WAIT Peripheral 16 Interface RD/WR 16 P0:0 P0:1 Addr Addr 16 Gen P1:0 Gen P1:1 Program Unit0 Unit1 P2:0 P2:1 Control Unit HALT 816 8 VAHI RESET DDATA AN0 Bank 16 CLKI 16 AN1 Switch 8-Bit CLKO AN2 A/D 16 16 16 16 MSB AN3 VALO Port 1 Phase XY Stack LPF Locked P1.0 or INT2 Multiplier Loop P1.1 or CLKOUT P P1.2 or SDI P1.3 or SDO 8-Bit I/O 16 MSB P1.4 or SS 24 P1.5 or SCLK V Shifter DD P1.6 or UI0 V P1.7 or UI1 SS 16 24 AV CC Port 2 16-Bit Counter AGND MUX Timer P2.0 or INT0 P2.1 or INT1 24 24 16-Bit Counter P2.2 or TMO0 Timer, PWM P2.3 or TMO1 ALU 8-Bit I/O P2.4 or WAIT 24 16-Bit Counter P2.5 or UI2 Timer, PWM P2.6 or TMO2 Accumulator P2.7 24 16 MSB SPI P3.7P3.4 4 Inputs 4 Outputs P3.3P3.0 Figure 1. Z892X3/3x3 Functional Block Diagram 2 DS000202-DSP0599 PADDR PDATA DDATA0 DADDR0 DDATA1 DADDR1