AS4C128M16D2 Revision History AS4C128M16D2- 84-ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet March 2014 Rev 2.0 Amended page 74 corrected package dimensions October 2014 to be E and S to be SE Rev 3.0 Amended page 1 : B: indicates 60-ball changed to 84-ball August 2017 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice. Version 3.0 - August 2017 Confidential 0 AS4C128M16D2 128M x 16 bit DDRII Synchronous DRAM (SDRAM) Confidential Advanced (Rev. 2.0, October. /2014) Features Description - High speed data transfer rates with system frequency up The AS4C128M16D2 is an eight bank DDR DRAM organized to 400 MHz as 8 banks x 16Mbit x 16. The AS4C128M16D2 achieves high - 8 internal banks for concurrent operation speed data transfer rates by employing a chip architecture - 4-bit prefetch architecture that prefetches multiple bits and then synchronizes the - Programmable CAS Latency: 3, 4 ,5 , 6 and 7 output data to a system clock. - Programmable Additive Latency: 0, 1, 2, 3 , 4, 5 and 6 The chip is designed to comply with the following key - Write Latency = Read Latency -1 DDR2 SDRAM features:(1) posted CAS with additive latency, - Programmable Wrap Sequence: Sequential or (2) write latency = read latency-1, (3) On Die Termination. Interleave All of the control, address, circuits are synchronized - Programmable Burst Length: 4 and 8 with the positive edge of an externally supplied clock. I/O s - Automatic and Controlled Precharge Command are synchronized with a pair of bidirectional strobes - Power Down Mode (DQS, DQS) in a source synchronous fashion. - Auto Refresh and Self Refresh - Refresh Interval: 7.8 us (8192 cycles/64 ms) Tcase Operating the eight memory banks in an interleaved fashion allows random access operation to occur at a between 0C and 85C - ODT (On-Die Termination) higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on - Weak Strength Data-Output Driver Option - Bidirectional differential Data Strobe (Single-ended burst length, CAS latency and speed grade of the device. data-strobe is an optional feature) - On-Chip DLL aligns DQ and DQs transitions with CK transitions - DQS can be disabled for single-ended data strobe - Differential clock inputs CK and CK - JEDEC Power Supply 1.8V 0.1V - VDDQ =1.8V 0.1V - Available in 84-ball FBGA - RoHS compliant - PASR Partial Array Self Refresh - tRAS lockout supported Table 1. Ordering Information Part Number Clock Frequency Data Rate Power Supply Package AS4C128M16D2-25BCN 400MHz 800Mbps/pin VDD 1.8V, VDDQ 1.8V 84 ball FBGA AS4C128M16D2-25BIN 400MHz 800Mbps/pin VDD 1.8V, VDDQ 1.8V 84 ball FBGA B: indicates 84-ball 8 x 10 x 1.2mm (max) FBGA package C: indicates commercial temperature I: indicates industrial temperature N: indicates Pb and Halogen Free ROHS Table 2. Speed Grade Information Speed Grade Clock Frequency CAS Latency t (ns) t (ns) RCD RP DDR2-800 400 MHz 5 5 5 Confidential 1 Version 3.0 - August 2017