AS4C128M16D3-12BAN Alliance Memory

2Gb Auto-AS4C128M16D3 Revision History 2Gb Auto-AS4C128M16D3 - 96 ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet May 2015 Rev 2.0 1 Delete Truth Table Note 5 Device state is 4 and 8 burst operation. Apr 2016 . Add follow information in Absolute Maximum DC Ratings note2 2 Recommended storage temperature is not exceeding 105C. Do not store at 150C for more than 1000 hours. Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1/83 - Rev.2.0 April 20162Gb Auto-AS4C128M16D3 Features Overview JEDEC Standard Compliant The 2Gb Double-Data-Rate-3 DRAMs is double data rate architecture to achieve high-speed Power supplies: V & V = +1.5V 0.075V DD DDQ operation. It is internally configured as an eight bank Operating temperature: -40~105 (TC) DRAM. AEC-Q100 Compliant The 2Gb chip is organized as 16Mbit x 16 I/Os x 8 Supports JEDEC clock jitter specification bank devices. These synchronous devices achieve Fully synchronous operation high speed double-data-rate transfer rates of up to Fast clock rate: 800MHz 1600 Mb/sec/pin for general applications. Differential Clock, CK & CK The chip is designed to comply with all key DDR3 Bidirectional differential data strobe DRAM key features and all of the control and address inputs are synchronized with a pair of externally - DQS & DQS supplied differential clocks. Inputs are latched at the 8 internal banks for concurrent operation cross point of differential clocks (CK rising and CK 8n-bit prefetch architecture falling). All I/Os are synchronized with differential DQS Pipelined internal architecture pair in a source synchronous fashion. Precharge & active power down These devices operate with a single 1.5V Programmable Mode & Extended Mode register 0.075V power supply and are available in BGA Additive Latency (AL): 0, CL-1, CL-2 packages. Programmable Burst lengths: 4, 8 Burst type: Sequential / Interleave Output Driver Impedance Control 8192 refresh cycles / 64ms - Average refresh period 7.8s -40 TC +85 3.9s +85TC +10 5 Write Leveling ZQ Calibration Dynamic ODT (Rtt Nom & Rtt WR) RoHS compliant Auto Refresh and Self Refresh 96-ball 9 x 13 x 1.2mm FBGA package - Pb and Halogen Free Table 1. Speed Grade Information Speed Grade Clock Frequency CAS Latency t (ns) t (ns) RCD RP 13.75 13.75 800 MHz 11 DDR3-1600 Table 2. Ordering Information Product part No Org Temperature Max Clock (MHz) Package 800 AS4C128M16D3-12BAN 128M x 16 Automotive -40C to 105C 96-ball FBGA Confidential - 2/83 - Rev.2.0 April 2016