AS4C128M16D3LA-12BIN Alliance Memory

AS4C128M16D3LA-12BIN Revision History 2Gb AS4C128M16D3LA-12BIN - 96 ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet May. 2016 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential -183- Rev. 1.0 May 2016AS4C128M16D3LA-12BIN 128M x 16 bit DDR3L Synchronous DRAM (SDRAM) Features Overview JEDEC Standard Compliant The 2Gb Double-Data-Rate-3 (DDR3L) DRAMs is double data rate architecture to achieve high-speed Power supplies: V & V = 1.35V DD DDQ operation. It is internally configured as an eight bank Backward compatible to V & V = 1.5V 0.075V DD DDQ DRAM. Industrial temperature: TC = -40~95 C The 2Gb chip is organized as 16Mbit x 16 I/Os x 8 Supports JEDEC clock jitter specification bank devices. These synchronous devices achieve Fully synchronous operation high speed double-data-rate transfer rates of up to Fast clock rate: 800MHz 1600 Mb/sec/pin for general applications. The chip is designed to comply with all key DDR3L Differential Clock, CK & CK DRAM key features and all of the control and address Bidirectional differential data strobe inputs are synchronized with a pair of externally supplied - DQS & DQS differential clocks. Inputs are latched at the cross point 8 internal banks for concurrent operation of differential clocks (CK rising and CK falling). All 8n-bit prefetch architecture I/Os are synchronized with differential DQS pair in a Pipelined internal architecture source synchronous fashion. Precharge & active power down These devices operate with a single 1.35V -0.067V /+0.1V power supply and are available in FBGA packages. Programmable Mode & Extended Mode registers Additive Latency (AL): 0, CL-1, CL-2 Programmable Burst lengths: 4, 8 Burst type: Sequential / Interleave Output Driver Impedance Control 8192 refresh cycles / 64ms - Average refresh period 7.8s -40 C TC +85 C 3.9s +85 C TC +95 C Write Leveling ZQ Calibration Dynamic ODT (Rtt Nom & Rtt WR) RoHS compliant Auto Refresh and Self Refresh 96-ball 8 x 13 x 1.0mm FBGA package - Pb and Halogen Free Table 1. Ordering Information Temperature Max Clock (MHz) Product part No Org Package 800 96-ball FBGA AS4C128M16D3 LA-12BIN 128M x 16 Industrial -40C to 95C Table 2. Speed Grade Information Speed Grade Clock Frequency CAS Latency t (ns) t (ns) RCD RP 13.75 13.75 800 MHz 11 DDR3L-1600 Confidential -283- Rev. 1.0 May 2016