AS4C128M16D3LC-12BAN Alliance Memory

AS4C128M16D3LC-12BAN Revision History 2G DDR3L SDRAM 96ball FBGA Package Revision Details Date Rev 1.0 Preliminary datasheet Jun. 2019 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1 of 86 - Rev.1.0 June 2019AS4C128M16D3LC-12BAN 128M x 16 bit DDR3L Synchronous DRAM (SDRAM) Advance (Rev. 1.0, Jun. /2019) Features Overview JEDEC Standard Compliant The 2Gb Double-Data-Rate-3L (DDR3L) DRAMs is double data rate architecture to achieve high-speed AEC-Q100 Compliant operation. It is internally configured as an eight bank Power supplies: V & V = +1.35V (1.283V ~ 1.45V) DD DDQ DRAM. Backward compatible to V & V = +1.5V 0.075V DD DDQ The 2Gb chip is organized as 16Mbit x 16 I/Os x 8 bank Operating temperature: T = -40~105 C (Automotive) C devices. These synchronous devices achieve high speed Supports JEDEC clock jitter specification double-data-rate transfer rates of up to 1600 Mb/sec/pin Fully synchronous operation for general applications. The chip is designed to comply with all key DDR3L Fast clock rate: 800MHz DRAM key features and all of the control and address Differential Clock, CK & CK inputs are synchronized with a pair of externally supplied Bidirectional differential data strobe differential clocks. Inputs are latched at the cross point - DQS & DQS of differential clocks (CK rising and CK falling). All I/Os 8 internal banks for concurrent operation are synchronized with differential DQS pair in a source 8n-bit prefetch architecture synchronous fashion. Pipelined internal architecture These devices operate with a single 1.35V -0.067V / Precharge & active power down +0.1V power supply. Programmable Mode & Extended Mode registers Additive Latency (AL): 0, CL-1, CL-2 Programmable Burst lengths: 4, 8 Burst type: Sequential / Interleave Output Driver Impedance Control Average refresh period - 8192 cycles/64ms (7.8us at -40C T +85C) C - 8192 cycles/32ms (3.9us at +85C T +95C) C - 8192 cycles/16ms (1.95us at +95C T +105C) C Write Leveling ZQ Calibration Dynamic ODT (Rtt Nom & Rtt WR) RoHS compliant Auto Refresh and Self Refresh - Not support self refresh function with T > 95C C Package: Pb and Halogen Free - 96-ball 7.5 x 13 x 1.0mm FBGA Table 1. Ordering Information Org Temperature Product part No Max Clock (MHz) Package 800 128M x 16 Automotive -40C to 105C 96-ball FBGA AS4C 128M16D3 LC-12B AN Table 2. Speed Grade Information Speed Grade Clock Frequency CAS Latency t t (ns) (ns) RCD RP 800 MHz 11 13.75 13.75 DDR3 L-1600 Confidential - 2 of 86 - Rev.1.0 June 2019