AS4C128M16MD2A-25BIN Alliance Memory

AS4C64M32MD2A-25BIN AS4C128M16MD2A-25BIN Revision History 2G (128M x 16 and 64M x 32) Low Power DDR 2 SDRAM 134ball FBGA Package AS4C 128M16MD2A-25BIN/AS4C 64M32MD2A-25BIN Revision Details Date Rev 1.0 Preliminary datasheet Jan 2018 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1 of 125 - Rev.1.0 Jan. 2018AS4C64M32MD2A-25BIN AS4C128M16MD2A-25BIN DDR2 Sync DRAM Features Functionality Configuration - VDD2 = 1.141.30V - 128 Meg X 16 (16 Meg X 16 X 8 Banks). - VDDCA/VDDQ = 1.141.30V - 64 Meg X 32 (8 Meg X 32 X 8 Banks). - VDD1 = 1.701.95V Low Power Features - Interface : HSUL 12 - Low voltage power supply. - Data width : x16 / x32 - Auto TCSR (Temperature Compensated Self Refresh). - Clock frequency range : max 400MHz - PASR (Partial Array Self Refresh) power-saving mode. - Four-bit pre-fetch DDR architecture - DPD (Deep Power Down) Mode. - Eight internal banks for concurrent operation - DS (Driver Strength) Control. - Multiplexed, double data rate, command/address inputs Timing Cycle time commands entered on every CK edge - 1.875ns RL = 8 - Bidirectional/differential data strobe per byte of -2.5ns RL = 6 data(DQS/DQS ). -3.0ns RL = 5 - DM masks write date at the both rising and falling edge of Operating Temperature Ranges the data strobe - Industrial (-40 to +85). - Programmable READ and WRITE latencies (RL/WL) Package - Programmable burst lengths: 4, 8, or 16 - 134-Ball FBGA(10.0mm x 11.5mm x 1.0mm) - Auto refresh and self refresh supported - All bank auto refresh and per bank auto refresh supported - Clock stop capability Table 1. Ordering Information Product Part No. Org. Temperature Max Clock (MHz) Package -40C to 85C 134-ball FBGA AS4C128M 16MD2A-25BIN 128M x 16 400 -40C to 85C 134-ball FBGA AS4C64M32MD2A-25BIN 64M x 32 400 Table 2. Speed Grade Information Speed Grade Clock Frequency RL WL t (ns) t (ns) RCD RP 400 MHz DDR2L-800 6 3 18 18 Confidential - 2 of 125 - Rev.1.0 Jan. 2018